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4th International Conference and Exhibition on
Device Packaging

www.imaps.org/devicepackaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA



Conference and Technical Workshops
March 17-20, 2008
Exhibition and Technology Showcase
March 18-19, 2008
Professional Development Courses
March 17, 2008
GBC Spring Conference
March 16-17, 2008

Device Packaging Advance Program
Register On-Line | Hotel Information

EARLY REGISTRATION AND HOTEL DEADLINES:
FEBRUARY 14, 2008


Professional Development Courses (PDCs)

Fundamentals of Packaging of MEMS and Related Microsystems and Nanomanufacturing (PDC1)
Hermeticity Testing and “Near Hermetic” Packaging (PDC2)
Package on Package (PoP) Applications, Requirements, Infrastructure and Technologies (PDC3)
Packaging Issues & Solutions for MEMS, MOEMS, and Nanoelectronics (PDC4)
Area Array Microelectronics Package Reliability (PDC5)
Advances in 3D Integration and Packaging (PDC6)

Morning Professional Development Courses
8:00 am – Noon

Monday, March 17

Fundamentals of Packaging of MEMS and Related Microsystems and Nanomanufacturing (PDC1)
Course Leader: Ajay P. Malshe, University of Arkansas

Course Description:
Fabrication and application-specific packaging of micro electromechanical systems (MEMS) is a subject of immense interest. Their application-specific packaging with other components is challenging and unlike IC packaging, has a different set of demands from releasing, dicing-to-interconnection at chip-scale and manufacturing at wafer-level. This globally-taught course will address silicon and non-silicon micro fabrication processes and related design details, and packaging of silicon and non-silicon MEMS and related microsystems. The course will use a range of novel applications to advocate the use of various fabrication and packaging processes. The course will also introduce a new area on the horizon: “nano packaging - manufacturing.” In the broader scope of the subject, for the 21st century packaging community, infusion of signals (electrical, optical, chemical, mechanical, etc.), domains (hermetic, vacuum, fluidic, optical, etc.) and scales (nano-to-micro-macro) are of significant importance for designing and developing next generation engineered micro and nano products as well as for adding value / functions to existing products. Particularly, key words, namely MEMS, micro systems and nano technologies have captured attention of technology leaders. MEMS and related micro systems are typically divided into two application areas: sensors and actuators. These are applied for a range of applications such as automotive, biomedical, optical, RF, etc. Examples of systems, devices and related application-specific packages are accelerometers, gyros, DMDTM, lab-on-a-chip, SMART drugs, etc. Further, with the major investment and key advancements in nanotechnology, nano integrated MEMS and related micro devices and packages are of major importance to the next generation engineered electronic systems.

Course Notes:
(1) Chapter “Packaging of MEMS and MOEMS: Challenges and A Case Study” by Drs. Malshe and O’Conner, (2) copies of the transparencies on MEMS and Nanomanufacturing, and (3) publication-“NSF-EC Workshop on Nanomanufacturing and Processing: A Summary Report,” Malshe et al., SPIE International Symposium on Smart Materials, Nano-, and Micro-Smart Systems, Melbourne, Australia, December 2002.

Specific Topics Covered:

  • Introduction to MEMS and Related Microsystems
  • Fundamentals of silicon and other related micro fabrication techniques
  • Introduction to M4 in comparison to MEMS
  • Nontraditional micro fabrication processes, such as femtosecond laser and micro EDM processing
  • Introduction to applications of MEMS and related microsystems and application-specific packaging
  • System-on-a-chip vs. system-in-a-package: challenges and trade-offs for MEMS packaging
  • IC packaging vs. MEMS packaging: differences and similarities
  • Packaging and assembly of MEMS and related micro devices: role of die release, handling, dicing, attachment, interconnections, outgassing, encapsulation, wafer-level packaging, etc., for application-specific MEMS and related microsystem packaging
  • Wafer-level and chip scale packaging of MEMS and related microsystems
  • Implementation of MEMS to RF, fluidics, sensors, and related applications
  • Manufacturing of related products and markets
  • Nanopackaging and Integration
  • Q & A Session
Who Should Attend?
The course is meant for industry and academic leaders and investors in science and engineering with interest in MEMS and related micro and nano systems. Highly recommended for R&D scientists, engineers and managers involved in sensors, actuators, instrumentation and systems related to micro and nano systems technology. Graduate students with special interest in the above areas will also find it useful.

Ajay P. Malshe (Ph.D., 1992) is the 21st Century Endowed Chair Professor of Materials, Manufacturing Processes and Integrated Systems at the Department of Mechanical Engineering and adjunct-faculty of Electrical Engineering as well as Microelectronics and Photonics Program. He is Director of the Materials and Manufacturing Research Laboratories (MMRL; a cluster of 5 laboratories). Malshe has multidisciplinary research programs in the field of MEMS and microelectronics packaging and integration, nanomanufacturing and surface engineering for advanced machining. He has authored over one hundred twenty-five peer-reviewed publications, four book chapters, and holds seven patents. His landmark scientific and engineering contributions are nano-particle composite coatings, particularly cubic boron nitride - titanium nitride composite coating (cBN-TiN), electric discharge machining (electric pen lithography-EPL), wafer level chip scale packaging of MEMS and related microsystems, nano stamping of quantum structures, nano-mechanical machining system-on-a-chip, chemo-mechanical as well as laser polishing of diamond films, femtosecond laser for chemically clean nano and micro machining of difficult-to-machine materials. He has received sixteen awards for research, education and service achievements (1996-2006). The most recent prestigious recognitions, Frost & Sullivan 2005 Technology Excellence Award and 2006 Top 25 Micro and Nano Innovations from R&D Magazine and Micro/Nano Newsletter are due to his team’s invention contribution in the area of nanocomposite coating. He is a Fellow of Institute of Physics, London, UK and is listed in Lexington’s Who’s Who. He has graduated over twenty-five graduate students (PhD/MS), trained numerous post-doctoral fellows, and provided research experience to several undergraduate and high school students. He has an extensive track record of global collaborations with academic institutions and companies. Prof. Malshe is the Chief Technology Officer (CTO) of the two companies he has co-founded in the fields of nanomanufacturing (NanoMech LLC; www.nanomech.biz) and high-density Microsystems packaging (OmniPak LLC) in the state of Arkansas. He is a member of professional societies such as ASEE, ASME, IEEE, IMAPS, MRS and SME and has arranged and chaired sessions and symposia in the areas of his expertise.

Hermeticity Testing and “Near Hermetic” Packaging (PDC2)
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
Hermeticity of electronics packages and hermeticity test techniques continue to be of critical importance to the microelectronics packaging community.  Specifically, for MEMS, OLEDs, wafer scale packaging, optoelectronic devices, bio-medical implants and packaging for military and space.  In contrast to a hermetic cavity-style package "near hermetic" packages are being developed that rely on polymeric materials, such as LCP, to produce a package with just enough moisture protection to survive in the intended end-use environment.

This course begins with an overview of hermetic sealing processes.  The class will then examine the accepted leak test techniques as prescribed in Mil Standard 883 Test Method 1014. This misunderstood test method is often a source of frustration.  The basic science behind helium fine leak testing (both the fixed and flexible methods) will be presented. Difficulties and limitations in fine leak testing of small volume packages is a major industry concern, especially among the space community.

Recently techniques have been developed that measure both gross and fine leaks in the same pass. Optical Leak Test (OLT) is a method that employs a laser interferometer to measure out of plane deflection on a lid surface in response to a changing pressure and, relates these measurements to an equivalent helium leak rate.  Cumulative Helium Leak Detection (CHD) is a variation on conventional leak detection that allows for gross and fine leak testing in the same pass and the potential for helium leak detection at leak rates several orders of magnitude lower than that available with conventional leak detection methods.

Packages made from polymeric materials as opposed to traditional hermetic seals (i.e., metal, glasses, ceramics) require a different approach from a testing standpoint.  The problem is now one of moisture diffusion through the barrier and package interfaces.  A brief review of the techniques and methods to evaluate a "non-hermetic" approach is presented.

In addition to a comprehensive set of course notes, each student receives a copy of  “Hermeticity of Electronic Packages” by Hal Greenhouse (Noyce Publications 2000) and a "Practical Guide to TM 1014" authored by the Instructor.

Who Should Attend?          
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA results and for those responsible for evaluating package designs requiring hermetic or "near hermetic" packages.

Thomas J. Green is the Principal at TJ Green Associates LLC, a Veteran owned small business devoted to providing world class teaching and consulting services in microelectronics packaging. As an independent consultant Tom's been responsible for numerous successful projects in the area of wirebond, die attach and package seal and associated leak test. As an Adjunct Professor at the National Training Center for Microelectronics he designs curriculum and teaches industry short courses relating to advanced microelectronics manufacturing processes. He has over twenty-five years of experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. Tom is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

Package on Package (PoP) Applications, Requirements, Infrastructure and Technologies (PDC3)
Course Leader: Moody Dreiza, Amkor Technology

Course Description:
This course will take an in-depth view of the applications, market requirements, supply chain infrastructure and technologies associated with the BGA package stacking platform commonly referred to as package on package (PoP).

This course will help you decide when and how PoP technology can provide system level semiconductor integration benefits; how you can evaluate and select the optimum PoP technology for your applications by understanding the complex mix of cost, performance and business / logistic benefits PoP provides; where industry standards, device floor-planning and supply chain infrastructures can reduce the total cost or time to market when implementing a PoP solution; how the PoP platform aligns with industry roadmaps to meet the higher density challenges associated with next generation device integration and system design requirements; and what the key PoP design related parameters are and how they relate to package sizing and selection.

PoP Technologies and Infrastructure covered will include:
The top PoP which is typically a memory component using stacked die multi-chip package technology to integrate a combination of memory devices.  Associated JEDEC memory interface standards will be highlighted.

The bottom PoP which is typically a logic component using advanced high density thin core substrate technology with special design and material properties to enable integration of a high density mobile processor device and support stacking of combination memory top package.  Enabling technologies, and JEDEC mechanical design guidelines will be summarized.

The PoP infrastructure - including SMT stacking, pre-stacking and joint industry studies for stacking and board level reliability testing will be presented.

A section of the course will review real world high volume PoP applications used in multimedia mobile handsets based on industry teardown reports. Quantify the technical and business / logistic factors that make up the total cost of ownership benefits which has been major driver of broad industry adoption of the PoP technology.

The course will explore the critical role industry infrastructure development and JEDEC standards have played in the high rates of PoP adoption in mobile multimedia applications.

Who Should Attend?
Engineers, Scientists and Managers involved with or interested in learning about applications, market requirements, supply chain infrastructure and technologies associated with the BGA package stacking platform commonly referred to as package on package (PoP).

Moody Dreiza’s current responsibilities are in the field of product management associated with Amkor Technology’s stacked package (PoP) product line. Moody’s previous experience includes four years in Amkor’s design center supporting CSP and PBGA design and design tool automation. Moody has earned a Bachelor’s degree in Mechanical Engineering from the University of Manchester Institute of Science and Technology (UMIST) in Manchester, England.

Break: 10:15 am – 10:30 am


Afternoon Professional Development Courses
1:00 pm – 5:00 pm

Packaging Issues & Solutions for MEMS, MOEMS, and Nanoelectronics (PDC4)
Course Leader: Ken Gilleo, ET-Trends LLC

Course Description:
This new course provides an overview of MEMS (Micro-Electro-Mechanical Systems), MOEMS (aka Optical-MEMS) and Nanotechnology packaging strategies and technologies. Topics include package designs, materials, and processes for these three related device technologies. MEMS and MOEMS devices face considerable packaging challenges. Special packaging requirements will be covered in detail and a variety of options offered with a cost-reduction focus. Package types include metal, ceramic, wafer-level, non-hermetic plastic and near-hermetic injection molded cavity. Hermeticity measurement, criteria, acceptable levels, and issues are discussed. In-package and on-chip “packaging agents,” such as getters, molecular coatings, and volatile anti-stiction/lubricants, are included.

Packaging trends discussion encompasses cost-reduction with ceramic designs, hermetic capping to enable plastic overmolding, laser sealing, microinjection plastic cavity types, and the 100% WLP (wafer-level package). MEMS-specific commercial packaging information is provided and several successful case histories are described. Fluidic-MEMS, an important emerging area, is discussed including fluidic coupling and “pluggable” packaging.

Finally, requirements for future Nanotechnology devices will be predicted based on known properties of materials and the characteristics of experimental devices. The case will be made for the adoption of MEMS packaging for future Nanoelectronic devices. Find out if packaging Nanoelectronics will be a serious challenge or easier than expected - you may be surprised!

Who Should Attend?
Inventors, product developers, innovators, marketing personnel, analysts, equipment providers, and technologists in electronics, medical, biology, BioMed, analytical field, optoelectronics, materials, telecom systems, and military.

Dr. Ken Gilleo is a chemist, inventor, IP specialist, expert witness, writer and consultant in materials, printed circuits, plastic packaging, assembly and emerging technologies including MEMS, MOEMS and Nanotechnology. He developed getters, low cost plastic packages, adhesives and laser sealing for MEMS and MOEMS. He has produced over 500 articles, technical presentations and workshops and his 7th book, “MEMS/MOEMS Packaging” was published in late 2005. He has helped pioneer low-cost plastic packaging for MEMS and worked on packaging designs, materials and processes.

Area Array Microelectronics Package Reliability (PDC5)
Course Leader: Amaneh Tasooji, Arizona State University

Course Description:
The objective of this course is to provide an overview on area array package reliability, analysis and tools and bestow awareness on critical factors impacting microelectronics packaging reliability.

Area Array microelectronic packages with small pitch and large I/O count grid array are used in commercial and military applications such as in aerospace, medical, telecommunication, transportation, etc. Reliability and risk assessment analysis of these widely used packages is a critical element of product design and field support. Current practice in reliability focuses on thermal cycling of manufactured components and monitors the component failure under the accelerated test conditions (ATC) representing the factory and OEM assembly, shipping and storage, and on/off environment of most electronic products (user interface). Acceleration Factor (AF) is then determined using ATC data and the performance of the package under “use condition;” hence, the package service reliability is predicted by extrapolation and application of AF. Statistical methods and life prediction methodologies are used in conjunction with local/global elastic and/or inelastic stress/strain analysis in component reliability assessment.

This course briefly reviews Area Array design and discusses reliability approach, analysis and tools. Solder joint reliability is discussed in detail by reviewing the published ball grid and column grid array (BGA/CGA) data, and evaluating the impact of various parameters (e.g., materials, design, and processing parameters) on it. Deformation and failure mechanisms influencing reliability of solder joints are discussed in detail and current life prediction models and failure modes such as brittle/ductile fracture, creep, fatigue, corrosion, and over-aging are discussed to further extend and reinforce the intended learning. Solder joint microstructure and the Inter-Metallic Compounds (IMC) evolutions that may take place during thermal processing and/or product application (isothermal and cyclic aging), and their impact on reliability are discussed by reviewing the Optical and Scanning Electron Microscopy images and characterization data.
 
Who should attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with area array packages and general device assembly technologies.

Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering, manufacturing, and e-business. She received her Ph.D. in Materials Science and Engineering from Stanford University in 1982 and has a B.S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, component design, manufacturing, quality, and supply chain in many industries such as microelectronics, aerospace, and nuclear. She has had many technical and leadership responsibilities while at Honeywell/AlliedSignal and has developed many materials behavior, deformation, and fracture models to improve life prediction and design capabilities, thereby increasing product reliability. Dr. Tasooji is the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. She holds a patent on “Adaptive Knowledge Management System for Vehicle Trend Monitoring, Health Management and Preventive Maintenance,” and has technical licenses for computer software on “Predicting Stress Corrosion Cracking in Nuclear Fuel Rods.” Dr. Tasooji has developed and delivered many graduate engineering courses (e.g., “Introduction to Micro-electronic Packaging,” “Overview of Materials Science and Engineering for Microelectronics Packaging,” “Advanced Packaging Analysis and Design: Material Considerations,” and “Nuclear Materials”) and many undergraduate courses (e.g., “Structure and Properties of Materials” and “Physical Metallurgy”) at Arizona State University. She has leveraged new technology and e-learning concepts in developing web-based learning tools to be used in conjunction with face-to-face teaching, while emphasizing an Interactive Learning concept.

Advances in 3D Integration and Packaging (PDC6)
Course Leader: Prof. James Jian-Qiang Lu, Rensselaer Polytechnic Institute

Course Description:
An overview of 3D integration and packaging will be presented, including motivation, key technologies and status towards commercialization.  The major motivations discussed include miniaturization of micro-systems; performance increase in speed and data bandwidth due to massive small-sized inter-chip interconnects; heterogeneous system integration of variety of technologies; and lower manufacturing cost for specific applications using particular 3D platforms.

In this course, 3D integration technologies are divided into 4 categories – transistor build-up, wafer-to-wafer stack, die-on-wafer assembly, and packaging-based 3D. In transistor build-up 3D, active devices are built-up over an IC wafer. In wafer-to-wafer stack 3D, different systems are first fabricated independently and then stacked and interconnected vertically. The die-on-wafer assembly is similar to a SoC approach, but with known-good-dies (KGDs) assembled on an IC wafer, then processed in wafer-level. In the last category, the ICs are packaged vertically in die-to-die, system-in-packaging (SiP) and package-on-package (PoP) fashions.

This course will discuss all these technologies, with emphasis on technology status and potential applications. The issues associated with each technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented, showing 3D hyper-integration as a very promising emerging architecture for future computer, network, nanotech, and biotech.

Who Should Attend?
Engineers, managers and executives involved in future R&D investments, assembly and product development of electronic packaging, and wanting fundamental understanding of 3D technologies, as well as the materials and equipment suppliers wanting to know about the existing and future 3D integration technologies and options, will greatly benefit from this course.

James Jian-Qiang Lu received his Dr. rer. nat. (Ph.D.) degree from Technical University of Munich in December 1995, and is currently an Associate Professor in Electrical Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY. At RPI, he has been leading the Interconnect Focus Center (IFC) flagship research program of 3D hyper-integration technology since 1999, and several other programs with focus on hyper-integration and micro-nano-bio interfaces for future chips. He has authored/co-authored more than 160 publications in refereed journals, conferences or books, and given a number of invited presentations, seminars and short courses. Dr. Lu also served as technical chair, workshop chair, session chair, panelist and panel moderator for many conferences. He is a senior member of IEEE (EDS & CPMT), a member of APS, MRS, ECS, and a member of IMAPS National Technical Committee (Chair of 3D Packaging).

Break: 2:30 pm – 2:45 pm


Corporate
Sponsors:


Corporate Sponsor - Ticona Engineering Polymers

Corporate Sponsor - NEXX Systems



Student Paper Competition
Sponsors:


Student Paper Competition Sponsor - Nordson

Student Paper Competition Sponsor - The Microelectronics Foundation




Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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