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5th International Conference and Exhibition on
Device Packaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA

Conference and Technical Workshops
March 10-12, 2009
Exhibition and Technology Showcase
March 10-11, 2009
Professional Development Courses
March 9, 2009
GBC Spring Conference
March 8-9, 2009

Device Packaging Advance Program
Register On-Line | Hotel Information

FEBRUARY 6, 2009

Professional Development Courses (PDCs)

3D Integration: Technology, Applications & Markets for 3D Integrated Circuits (PDC 2)
High-Performance Thermal Management Materials (PDC 3)
Package on Package (PoP) Applications, Requirements, Infrastructure and Technologies (PDC 4)
Fundamentals of Packaging of MEMS and Related Microsystems and Nanomanufacturing (PDC 5)
3D Integration and Packaging Technologies, Assessment, Status and Applications (PDC 6)
Implementing Flip Chip Technology (PDC 7)

Morning Professional Development Courses
8:00 am – Noon
Monday, March 9

Area Array Microelectronics Package Reliability (PDC1)
Course Leader: Amaneh Tasooji, Arizona State University

PDC 1 Cancelled

3D Integration: Technology, Applications & Markets for 3D Integrated Circuits (PDC2)
Course Leader: Philip Garrou, Microelectronic Consultants of NC

Course Description:
3D IC Integration is without question the hottest topic in Microelectronics today. This course has been put together based on the author’s activity in this field for the past 5 years which has included direct programs with numerous companies in the industry, his weekly 3D blog “Perspectives From the Leading Edge" in Semiconductor International and editing the 2008 (2) volume Wiley-VCH text “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits.” The course will define and contrast 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning stacking and wire bonding to a BGA base). We will look at drivers for 3D integration including the electrical performance and economic issues that are about to end CMOS device shrinkage, and the miniaturization issues faced in today’s portable devices. We will then look at various proposed process sequences and the process unit operations necessary to fabricate 3D stacks. The processes sequences proposed by universities, institutes and commercial entities will be compared and contrasted and we will examine early adopter applications such as CIS [CMOS image sensors]; memory [DRAM and NAND]; memory on logic and heterogeneous integration. The course will end by looking at the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.

Who Should Attend?
The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain. In the next few years 3D integration will have a rippling effect through the microelectronics industry and those who are caught unaware will be sorry.

Dr. Garrou is a fellow of both IEEE (2001) and IMAPS (2000) and has served as President and Technical VP of IEEE CPMT and IMAPS. He is currently Editorial Advisor and 3D integration blogger ("Perspectives From the Leading Edge") for Semiconductor International. He has authored 3 microelectronic texts including: “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits,” Wiley-VCH, 2008 and "Enabling Technologies for 3D Integration" MRS Vol. 970, 2006. Dr. Garrou has been awarded the 2007 IEEE CPMT Sustained Technical Contributions Award for “ …25 years of leadership and technical contributions in thin film dielectric materials and microelectronic applications such as multichip modules, bumping and wafer level packaging, integrated passives, o-LEDs and most recently 3D integration" and the 2001 IMAPS WD Ashman Achievement Award for “... technical contributions to the Microelectronics Packaging Industry.”

High-Performance Thermal Management Materials (PDC3)
Course Leader: Carl Zweben, Thermal Management Materials Consultant

Course Description:
The need for advanced thermal management and packaging materials is highlighted in the iNEMI 2007 Roadmap. In response to this need, there have been revolutionary advances in the last few years. There are now many low-CTE, low-density materials with thermal conductivities up to 1700 W/m-K (over four times that of copper). Many are supplied by major corporations. Advanced materials can reduce component and system cost. They can tailor PCB CTE, potentially eliminating the need for underfill. They also can increase PCB thermal conductivity, allowing heat removal from the bottom, as well as the top of a chip. There is a large and increasing number of microelectronic and optoelectronic applications, including: substrates; PCBs; PCB cold plates; heat spreaders; heat sinks; thermal interface materials; microprocessor, RF and power packages; thermoelectric cooler heat sinks; laser diode and LED packages; plasma and LCD displays; photovoltaic packaging; and detectors. This course covers the large and increasing number of high-performance thermal management materials, including properties, manufacturing processes, applications, cost, lessons learned, typical development programs, and future directions, including carbon nanotubes. The course also discusses traditional thermal management materials, of which many packaging engineers are unaware.

Who Should Attend?
Engineers, scientists and managers involved in microelectronic, optoelectronic, photovoltaic and MEMS/MOEMS thermal management and packaging design, production and R&D; packaging and thermal materials suppliers.

Dr. Zweben, now an independent consultant, directed advanced thermal management and packaging materials R&D for over 30 years. He was formerly Advanced Technology Manager and Division Fellow at GE Astro Space, where he was the first to use Al/SiC and other advanced materials in microelectronic, optoelectronic and photovoltaic packaging, and developed low-CTE PCBs. Other affiliations have included Du Pont, Jet Propulsion Laboratory and the Georgia Tech NSF Packaging Research Center. He was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer-of-the-Year awards. He is a Life Fellow of ASME, a Fellow of ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely on advanced thermal management and packaging materials.

Package on Package (PoP) Applications, Requirements, Infrastructure and Technologies (PDC4)
Course Leader: Moody Dreiza, Amkor Technology

Course Description:
This course will help you decide when and how PoP technology can provide system level semiconductor integration benefits. How you can evaluate and select the optimum PoP technology for your applications by understanding the complex mix of cost, performance and business / logistic benefits PoP provides. Where industry standards, device floor-planning and supply chain infrastructures can reduce the total cost or time to market when implementing a PoP solution. How the PoP platform aligns with industry roadmaps to meet the higher density challenges associated with next generation device integration and system design requirements. What the key PoP design related parameters are and how they relate to package sizing and selection.

PoP Technologies and Infrastructure covered will include:
The top PoP which is typically a memory component using stacked die multi-chip package technology to integrate a combination of memory devices. The associated JEDEC memory interface standards will be highlighted.

The bottom PoP which is typically a logic component using advanced high density thin core substrate technology with special design and material properties to enable integration of a high density mobile processor device and support stacking of combination memory top package. Enabling technologies and JEDEC mechanical design guidelines will be summarized.

The PoP infrastructure - including SMT stacking, pre-stacking and joint industry studies for stacking and board level reliability testing will be presented.

A section of the course will review real world high volume PoP applications used in multimedia mobile handsets based on industry teardown reports. Quantify the technical and business / logistic factors that make up the total cost of ownership benefits which has been a major driver of broad industry adoption of the PoP technology.

The course will explore the critical role industry infrastructure development and JEDEC standards have played in the high rates of PoP adoption in mobile multimedia applications.

Who Should Attend?
Engineers, Scientists and Managers involved with or interested in learning about applications, market requirements, supply chain infrastructure and technologies associated with the BGA package stacking platform commonly referred to as package on package (PoP).

Moody Dreiza’s current responsibilities are in the field of product management associated with Amkor Technology’s stacked package (PoP) product line. Moody’s previous experience includes four years in Amkor’s design center supporting CSP and PBGA design and design tool automation. Moody has earned a Bachelor’s degree in Mechanical Engineering from the University of Manchester Institute of Science and Technology (UMIST) in Manchester, England.

Break: 10:00 am – 10:20 am

Afternoon Professional Development Courses
1:00 pm – 5:00 pm

Fundamentals of Packaging of MEMS and Related Microsystems and Nanomanufacturing (PDC5)
Course Leader: Ajay P. Malshe, University of Arkansas (HiDEC-MEEG)

Course Description:
Fabrication and application-specific packaging of micro electromechanical systems (MEMS) is a subject of immense interest. Their application-specific packaging with other components is challenging and unlike IC packaging, has a different set of demands from releasing, dicing to interconnection at chip-scale and manufacturing at wafer-level. This globally taught course will address silicon and non-silicon micro fabrication processes and related design details, and packaging of silicon and non-silicon MEMS and related microsystems. The course will use a range of novel applications to advocate the use of various fabrication and packaging processes. The course will also introduce a new area on the horizon nano packaging – manufacturing in the broader scope of the subject, for the 21st century packaging community infusion of signals (electrical, optical, chemical, mechanical, etc.), domains (hermetic, vacuum, fluidic, optical, etc.) and scales (nano-to-micro-macro) are of significant importance for designing and developing next generation engineered micro and nano products as well as for adding value / functions to the existing products. Particularly, key words namely MEMS, micro systems and nano technologies have captured attention of technology leaders. MEMS and related micro systems are typically divided into two application areas: sensors and actuators. These are applied for a range of applications such as automotive, biomedical, optical, RF, etc. Examples of systems, devices and related application specific packages, are accelerometers, gyros, DMDTM, lab-on-a-chip, SMART drugs, etc. Further, with the major investment and key advancements in nanotechnology, nano integrated MEMS and related micro devices and packages are of major importance to the next generation engineered electronic systems.

Course Notes:
(1) Chapter “Packaging of MEMS and MOEMS: Challenges and A Case Study” by Drs. Malshe and O’Conner, (2) copies of the transparencies on MEMS and Nanomanufacturing, and (3) publication “NSF-EC Workshop on Nanomanufacturing and Processing: A Summary Report,” Malshe et al., SPIE International Symposium on Smart Materials, Nano, and Micro-Smart Systems, Melbourne, Australia, December 2002.

Who Should Attend?
The course is meant for industry and academic leaders and investors in science and engineering with interest in MEMS and related micro and nano systems. Highly recommended for R&D scientists, engineers and managers involved in sensors, actuators, instrumentation and systems related to micro and nano systems technology. Graduate students with special interest in the above areas will also find it useful.

Ajay P. Malshe (Ph.D., 1992) is the 21st Century Endowed Chair Professor of Materials, Manufacturing Processes and Integrated Systems at the Department of Mechanical Engineering and adjunct-faculty of Electrical Engineering as well as Microelectronics and Photonics Program. He is Director of the Materials and Manufacturing Research Laboratories (MMRL; a cluster of 5 laboratories). Malshe has multidisciplinary research programs in the field of MEMS and microelectronics packaging and integration, nanomanufacturing and surface engineering for advanced machining. He has authored over one hundred twenty-five peer-reviewed publications, four book chapters, and holds seven patents. His landmark scientific and engineering contributions are nano-particle composite coatings, particularly cubic boron nitride - titanium nitride composite coating (cBN-TiN), electric discharge machining (electric pen lithography-EPL), wafer level chip scale packaging of MEMS and related microsystems, nano stamping of quantum structures, nano-mechanical machining system-on-a-chip, chemo-mechanical as well as laser polishing of diamond films, femtosecond laser for chemically clean nano and micro machining of difficult-to-machine materials. He has received sixteen awards for research, education and service achievements (1996-2006). The most recent prestigious recognitions, Frost & Sullivan 2005 Technology Excellence Award and 2006 Top 25 Micro and Nano Innovations from R&D Magazine and Micro/Nano Newsletter are due to his team’s invention contribution in the area of nanocomposite coating. He is a Fellow of Institute of Physics, London, UK and is listed in Lexington’s Who’s Who. He has graduated over twenty-five graduate students (PhD/MS), trained numerous post-doctoral fellows, and provided research experience to several undergraduate and high school students. He has an extensive track record of global collaborations with academic institutions and companies. Prof. Malshe is the Chief Technology Officer (CTO) of the two companies he has co-founded in the fields of nanomanufacturing (NanoMech LLC; and high-density Microsystems packaging (OmniPak LLC) in the state of Arkansas. He is a member of professional societies such as ASEE, ASME, IEEE, IMAPS, MRS and SME and has arranged and chaired sessions and symposia in the areas of his expertise.

3D Integration and Packaging Technologies, Assessment, Status and Applications (PDC6)
Course Leader: Prof. James Jian-Qiang Lu, Rensselaer Polytechnic Institute

Course Description:
An overview of 3D integration and packaging will be presented, including motivation, key technologies and status towards commercialization. The major motivations discussed include miniaturization of micro-systems; performance increase in speed and data bandwidth due to massive small-sized Through-Strata-Vias (TSVs); heterogeneous system integration of variety of technologies; and lower manufacturing cost for specific 3D applications.

In this course, 3D integration technologies are divided into 4 categories – transistor build-up, wafer-to-wafer stack, die-on-wafer assembly, and packaging-based 3D. In transistor build-up 3D, active devices are built-up over an IC wafer. In wafer-to-wafer stack 3D, different systems are first fabricated independently and then stacked and interconnected vertically. The die-on-wafer assembly is similar to SoC approach, but with known-good-dies (KGDs) assembled on a wafer, then processed in wafer-level. In the last category, the ICs are packaged vertically in die-to-die, system-in-packaging (SiP) and package-on-package (PoP) fashions.

This course will discuss all these technologies, with emphasis on technology status and potential applications. The issues associated with each technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented, showing 3D hyper-integration as a very promising emerging architecture for future computer, network, nanotech, and biotech.

Who Should Attend?
Engineers, managers and executives involved in future R&D investments, assembly and product development of electronic packaging, and wanting fundamental understanding of 3D technologies, as well as materials and equipment suppliers wanting to know about existing and future 3D integration technologies and options, will greatly benefit from this course.

James Jian-Qiang Lu received his Dr. rer. nat. (Ph.D.) degree from Technical University of Munich in December 1995, and is currently an Associate Professor in Electrical Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY. At RPI, he has been leading the Interconnect Focus Center (IFC) flagship research program of 3D hyper-integration technology since 1999, and several other programs with focus on hyper-integration and micro-nano-bio interfaces for future chips. He has authored/co-authored more than 160 publications in refereed journals, conferences or books, and given a number of invited presentations, seminars and short courses. Dr. Lu also served as technical chair, workshop chair, session chair, panelist and panel moderator for many conferences. He is a senior member of IEEE (EDS & CPMT), a member of APS, MRS, ECS, and a member of IMAPS National Technical Committee (Chair of 3D Packaging).

Implementing Flip Chip Technology (PDC7)
Course Leader: R. Wayne Johnson, Auburn University

Course Description:
Flip chip use is growing in both flip chip-in-package and flip chip-on-laminate applications. This course will provide insight into the design and assembly of electronics using flip chip devices. The practical issues of implementing flip chip technology from wafer bumping to reliability characterization are covered. This course will begin with an examination of bumping options. Substrate requirements for flip chip will then be presented including a discussion of high density interconnect options and substrate design. Assembly of flip chip devices adds materials and processes to the standard SMT assembly process and the integration of these into the SMT process flow is examined. Materials and processes to be discussed include lead free alloys, fluxes, underfills (capillary flow, fluxing no-flow, and wafer applied), substrate dehydration, flux and underfill application, underfill curing, inspection, and underfill characterization techniques. The presentation will conclude with flip chip assembly reliability testing, test vehicle design and failure analysis.

Who Should Attend?
This PDC is intended for those individuals soon to be responsible for implementing flip chip assembly, suppliers of materials and equipment for flip chip assembly and others interested in flip chip implementation.

Dr. R. Wayne Johnson is a Professor of Electrical Engineering at Auburn University and Director of the Laboratory for Electronics Assembly and Packaging (LEAP). At Auburn, he has established teaching and research laboratories for advanced packaging and electronics assembly. Research efforts are focused on materials, processing, and reliability for advanced SMT, wire bond and flip chip assembly. He has published and presented numerous papers at workshops and conferences and in technical journals on flip chip assembly. Dr. Johnson is editor-in-chief of the IEEE Transactions on Electronics Packaging manufacturing and a Fellow of IMAPS and IEEE.

Hermeticity Testing, RGA and Near Hermetic Packaging Concepts (PDC8)
Course Leader: Thomas J. Green, TJ Green Associates LLC

PDC 8 Cancelled

Break: 3:00 pm – 3:20 pm

Welcome Reception (Device Packaging Conference)
5:00 pm - 7:00 pm


Corporate Sponsor - NEXX Systems

Student Paper Competition

Student Paper Competition Sponsor - The Microelectronics Foundation


Media Sponsor - Advanced Packaging

Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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