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6th International Conference and Exhibition on
Device Packaging

www.imaps.org/devicepackaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA



Conference and Technical Workshops
March 9-11, 2010
Exhibition and Technology Showcase
March 9-10, 2010
Professional Development Courses
March 8, 2010
GBC Spring Conference
March 7-8, 2010

In conjunction with the Global Business Council (GBC) Spring Conference, March 7-8


Courtesy of Rensselaer Polytechnic Institute

Courtesy of US Army RDEDCOM AMRDEC

General Chair:

Phil Garrou
Microelectronic Consultants of NC


3D Packaging
Topical Workshop
Flip Chip Technologies
Topical Workshop
Wafer Level Packaging
Topical Workshop
MEMS & Microsystems
Topical Workshop
Emerging Tech (LEDs & Passives)
Topical Workshop
Technical Co-Chair:
James J.-Q. Lu
Rensselaer Polytechnic Institute
Technical Co-Chair:
Linda Bal
Freescale Semiconductor
Technical Co-Chair:
Ted Tessier
FlipChip International
Technical Co-Chair:
Robert Dean
Auburn University
Technical Co-Chair:
Frank Wall
Philips
Technical Co-Chair:
Lee Smith
Amkor Technology
Technical Co-Chair:
Lou Nicholls
Amkor Technology
Technical Co-Chair:
Andrew Strandjord
Pac Tech USA
Technical Co-Chair:
Tracy Hudson
US Army
Technical Co-Chair:
Robert Heistand
AVX

Device Packaging Advance Program
Register On-Line | Hotel Information

EARLY REGISTRATION CUT-OFF: FEBRUARY 19, 2010
HOTEL DEADLINE: FEBRUARY 4, 2010


Professional Development Courses (PDCs)

3D Integration: Technology, Applications & Markets for 3D Integrated Circuits (PDC 1)
Area Array Microelectronics Package Reliability (PDC 2)
MEMS Reliability and Packaging (PDC 3)
3D Integration and Packaging Technologies, Assessment, Status and Applications (PDC 5)
Guide to Component Chip Attach - Including Flip Chip (PDC 6)
Near Hermetic Packaging Concepts for Military and Medical Devices (PDC 7)

Wire Bonding in Microelectronics (PDC 8)

Morning Professional Development Courses
8:00 am – Noon
Monday, March 8

3D Integration: Technology, Applications & Markets for 3D Integrated Circuits (PDC1)
Course Leader: Philip Garrou, Microelectronic Consultants of NC

Course Description:
3D IC Integration is without question the hottest topic in Microelectronics today. This course has been put together based on the author’s activity in this field for the past 5 years which has included direct programs with numerous companies in the industry, his weekly 3D blog “Perspectives From the Leading Edge" in Semiconductor International and editing the 2008 (2) volume Wiley-VCH text “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits.” The course will define and contrast 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning stacking and wire bonding to a BGA base). We will look at drivers for 3D integration including the electrical performance and economic issues that are about to end CMOS device shrinkage, and the miniaturization issues faced in today’s portable devices. We will then look at various proposed process sequences and the process unit operations necessary to fabricate 3D stacks. The processes sequences proposed by universities, institutes and commercial entities will be compared and contrasted and we will examine early adopter applications such as CIS [CMOS image sensors]; memory [DRAM and NAND]; memory on logic and heterogeneous integration. The course will end by looking at the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.

Who Should Attend?
The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain. In the next few years 3D integration will have a rippling effect through the microelectronics industry and those who are caught unaware will be sorry.

Dr. Garrou is a fellow of both IEEE (2001) and IMAPS (2000) and has served as President and Technical VP of IEEE CPMT and IMAPS. He is currently Editorial Advisor and 3D integration blogger ("Perspectives From the Leading Edge") for Semiconductor International. He has authored 3 microelectronic texts including: “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits,” Wiley-VCH, 2008 and "Enabling Technologies for 3D Integration" MRS Vol. 970, 2006. Dr. Garrou has been awarded the 2007 IEEE CPMT Sustained Technical Contributions Award for “ …25 years of leadership and technical contributions in thin film dielectric materials and microelectronic applications such as multichip modules, bumping and wafer level packaging, integrated passives, o-LEDs and most recently 3D integration" and the 2001 IMAPS WD Ashman Achievement Award for “... technical contributions to the Microelectronics Packaging Industry.”

Area Array Microelectronics Package Reliability (PDC2)
Course Leader: Amaneh Tasooji, Arizona State University

Course Description:
The objective of this workshop is to provide an overview on area array package reliability, analysis and tools and bestow awareness on critical factors impacting microelectronics packaging reliability.

Area Array microelectronic packages with small pitch and large I/O count grid array are used in commercial and military applications. Reliability and risk assessment analysis of these widely used packages is a critical element of product design and field support. Current practice in reliability focuses on thermal cycling of manufactured components and monitors the component failure under the accelerated test conditions (ATC) representing the factory and OEM assembly, shipping and storage, and on/off environment of most electronic products (user interface). Acceleration Factor (AF) is then determined using ATC data and the performance of the package under “use condition,” hence, the package service reliability is predicted by extrapolation and application of AF. Statistical methods and life prediction methodologies are used in conjunction with local/global elastic and/or inelastic stress/strain analysis in component reliability assessment.

This workshop briefly reviews Area Array design and discusses reliability approach, focusing on solder joints and reviewing the impact of various parameters (e.g., materials, design, and processing parameters) on joint reliability. Deformation and failure mechanisms influencing reliability of solder joints are discussed in detail.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with area array packages and general device assembly technologies.

Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering, manufacturing, and e-business. She received her Ph.D. in Materials Science and Engineering from Stanford University in 1982 and has a B.S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, component design, manufacturing, quality, and supply chain in many industries such as microelectronics, aerospace, and nuclear. She has had many technical and leadership responsibilities while at Honeywell/AlliedSignal and has developed many materials behavior, deformation, and fracture models to improve life prediction and design capabilities, thereby increasing product reliability. Dr. Tasooji is the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. She holds a patent on “Adaptive Knowledge Management System for Vehicle Trend Monitoring, Health Management and Preventive Maintenance,” and has technical licenses for computer software on “Predicting Stress Corrosion Cracking in Nuclear Fuel Rods.” Dr. Tasooji has developed and delivered many graduate engineering courses (e.g., “Introduction to Micro-electronic Packaging,” “Overview of Materials Science and Engineering for Microelectronics Packaging,” “Advanced Packaging Analysis and Design: Material Considerations,” and “Nuclear Materials”) and many undergraduate courses (e.g., “Structure and Properties of Materials” and “Physical Metallurgy”) at Arizona State University. She has leveraged new technology and e-learning concepts in developing web-based learning tools to be used in conjunction with face-to-face teaching, while emphasizing an Interactive Learning concept.

MEMS Reliability and Packaging (PDC3)
Course Leader: Slobodan Petrovic, Oregon Institute of Technology

Course Description:
From accelerometers to biomedical devices, from pressure sensors to optical displays, and from tunable lasers to DNA sensors, MEMS (Microelectromechanical systems) technology is becoming integral part of modern life. One of the biggest challenges hampering further progress of MEMS devices is the development of effective packaging solutions. Packaging provides protective housing and interface between the mechanical structure performing its intended function and the environment. Unlike electronic packaging where high density packaging methods have been developed, MEMS packaging evolution has been slow and not adequately meeting the diverse requirements of performance and reliability. As a result of great diversity in the type of MEMS devices the packaging considerations vary drastically not only from one device type to the next, but also among the different products in the same device category. For some devices like accelerometers, packaging must provide complete isolation from the surrounding, while for others such as DNA sensors it must enable intimate contact with the environment or optical transparency as in display devices. It is, therefore, not surprising that there are no standards in MEMS packaging and that universal solutions may not be possible.

The main purpose of packaging is to transform a micromachined structure or system into a useful device that performs its function and successfully communicates with the environment through electrical, fluidic, or optical connections. Packaging inevitably reduces the advantages of MEMS structure small size, it sometimes affects the performance, and it significantly adds to the overall cost of a MEMS device. It is a conservative estimate that packaging and testing are responsible, on average and depending on the device type, for 75% of the overall device cost. Consequently, one of the main challenges in MEMS manufacturing is to develop packaging solutions that meet the necessary performance and reliability criteria, while keeping the cost of assembly to minimum.

The intended outcome of the course is to provide a comprehensive overview of the MEMS packaging and reliability principles; with a particular emphasis on sensors and actuators used in industrial, medical, and automotive applications. Examples of these applications include accelerometers, pressure sensors, angular rate sensors, micropumps, valves, and thermal inkjet heads. The packaging discussion will also cover a wide range of other MEMS principles and devices such biological and chemical sensors, optical imaging and displays, as well as photonic applications used in the fiber-optics industry. These applications will be illustrated using examples such as lab-on-a-chip, DNA sensor, radiation imager, micromirror device, tunable laser, and wavelength locker. Three extensive case studies that will be used to most effectively demonstrate diverse packaging principles are: accelerometers, pressure sensors, and digital micromirror devices.

The seminar will be divided in 3 major sections: packaging design considerations, packaging types, and reliability and failure analysis.

Who Should Attend?
This is a survey course structured in such a way to provide a comprehensive overview of a broad array of packaging and reliability issues. While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will require a fairly detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field. Because each MEMS design deserves its own distinctive packaging approach, packaging considerations will be, whenever possible, illustrated using specific device examples; and every opportunity will be used to demonstrate the uniqueness of a packaging solution and its interaction with a micromachined structure. Using this dynamic teaching method, besides learning in depth about packaging and reliability, the participants will have the opportunity to gain knowledge about MEMS in general through the eyes of a packaging and reliability specialist.

Dr. Slobodan Petrovic is an associate professor in Electrical Engineering and Renewable Energy Department at Oregon Institute of Technology in Portland, OR, where he teaches solid state electronic devices, applied electromagnetic, fuel cells, batteries, and renewable energy. Prior to joining Oregon Institute of Technology, Dr. Petrovic was associate professor at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and nanocatalysts for energy applications. Prior to joining ASU Dr. Petrovic held appointments at Clear Edge Power (formerly Quantum Leap Technology) as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; industrial electrochemical processes; and catalysis. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

Addressing the Thermal Challenges in Stacked Die Packages with Advanced Thermal Interface Materials (TIMs) (PDC4)
Course Leader: Ron Hunadi, RJ Industries, LLC

CANCELLED

Break: 10:00 am – 10:20 am


Afternoon Professional Development Courses
1:00 pm – 5:00 pm

3D Integration and Packaging Technologies, Assessment, Status and Applications (PDC5)
Course Leader: James J.-Q. Lu, Rensselaer Polytechnic Institute

Course Description:
This course will discuss the latest development of Through-Strata-Vias (or Through-Si-Vias, TSVs) and other relevant enabling technologies for 3D IC integration and packaging. An overview of 3D integration and packaging will be presented, including motivation, key technologies and status towards commercialization. The major motivations discussed include miniaturization of micro-systems; performance increase in speed and data bandwidth due to massive small-sized TSVs; heterogeneous system integration of variety of technologies; and lower manufacturing cost for specific 3D applications.

In this course, 3D integration technologies are divided into 4 categories – transistor build-up, wafer-to-wafer (W2W) stack, chip-to-wafer (C2W) assembly, and packaging-based chip-to-chip (C2C) 3D. In transistor build-up 3D, active devices are built-up over an IC wafer. In W2W 3D stack, different systems are first fabricated independently and then stacked and interconnected vertically. The C2W assembly is similar to SoC approach, but with known-good-dies (KGDs) assembled on a wafer, then processed in wafer-level. In the last category, the ICs are packaged vertically in C2C, system-in-packaging (SiP) and package-on-package (PoP) fashions. A particular focus will be on various TSV fabrication/processing methods and applications, with relevant critical issues addressed, such as TSV processing, alignment, bonding, wafer thinning and handling for C2C, C2W and W2W integration platforms.

This course will discuss all these technologies, with emphasis on technology status and potential applications (e.g., image sensor, memory, and memory/logic). The issues associated with each technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented, showing 3D hyper-integration as a very promising emerging architecture for future computer, network, nanotech, and biotech.

Who Should Attend?
Professional engineers, technical managers and executives involved in future R&D investments, assembly and product development of electronic packaging, and wanting fundamental understanding of 3D technologies, as well as the materials and equipment suppliers wanting to know about the existing and future 3D integration technologies and options, will greatly benefit from this course. Scientists in research institutions, faculty members and postgraduate students in universities will learn the critical issues and possible solutions as well as research directions in 3D integration/packaging technologies and applications.

James Jian-Qiang Lu received his Dr. rer. nat. (Ph.D.) degree from Technical University of Munich in December 1995, and is currently an Associate Professor in Electrical Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY. At RPI, Dr. Lu worked with the Interconnect Focus Center (IFC) research program of 3D hyper-integration technology from 1999, and several other programs with focus on hyper-integration and micro-nano-bio interfaces for future chips. Dr. Lu has broad research experiences from micro-nano-electronics theory and design to materials, processing, devices, integration and packaging (e.g., GaAs, GaN and Si devices, novel FETs, terahertz electronics, carbon-nanotubes, and Si IC interconnects). He has authored/co-authored >200 publications, and gave a number of invited presentations, seminars and short courses. He served as technical chair, workshop chair, session chair, panelist and panel moderator for many conferences. He is a senior member of IEEE, a member of APS, MRS, and ECS. He has served as the 3D Packaging Chair of the IMAPS National Technical Committee since 2006. He received the 2008 IEEE CPMT Exceptional Technical Achievement Award in May 2008 “for his pioneering contributions to and leadership in 3D integration/packaging”.

Guide to Component Chip Attach - Including Flip Chip (PDC6)
Course Leader: Phillip Creter, Creter & Associates

Course Description:
This course provides an industry-proven training guide to successful component chip attach for use by engineers/senior technicians in a prototype or manufacturing environment. Students will learn various definitions, details of techniques, materials, processes and equipment used in traditional component chip attachment of passives (capacitors, inductors, resistors), actives (diodes, transistors, ICs) and rework methods. Topics covered include: SMT solder reflow, pick/place, dispensing, stamping, stencil printing, epoxy vs. eutectic, rework, and process control. Examples of actual process procedures and industry lot travelers are included. Special attention will be given to Flip Chip and Flip Chip packaging applications. Students will learn definitions (WLP, C4, UBM, ICA, ACA, UF & stud bumping), techniques, processes, materials, substrates and equipment used in flip chip die attachment and underfill using both solder and polymers. Included: types of wafer bumping, pick/place, solder reflow, polymer cure, underfilling, and process control methodology. Reliability testing and screening methods as well as analysis techniques for various types of component attach are discussed using optical, die shear, scanning electron microscopy and scanning acoustic microscopy. Operator issues include: setup, proper documentation, use of industry-proven lot travelers, inspection criteria, rework techniques and safety. Figures, photos and diagrams enhance the learning experience. Extensive references are included.

Who Should Attend?
Ideal for the senior engineers new to the field and needing a running start in chip attach or flip chip packaging technology. No prior knowledge is required since this course is designed for the student who has little initial familiarity with process and materials specifics of chip attach. The course uses simple terms for ease of understanding yet includes aspects of advanced packaging for more experienced engineers needing an update in technology. Also of value for people in quality assurance, sales, marketing, purchasing, safety, administration, and program management.

Phillip Creter has over 30 years of microelectronics packaging experience and is a Life member of IMAPS. He was elected a Fellow of the Society, National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry with honors from Suffolk University and has published numerous papers, holds a U.S. patent, has made many technical presentations (received Best Paper of Session award IMAPS) and chaired numerous technical sessions for symposia. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (receiving coveted corporate Lesley Warner Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer. Phil currently teaches professional development courses at microelectronics events and is an active certified instructor for the Department of Homeland Security.

Near Hermetic Packaging Concepts for Military and Medical Devices (PDC7)
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
Packages made from polymeric materials (e.g. LCP) as opposed to traditional hermetic seals (i.e. metals, glasses, ceramic etc) require a different approach from a hermeticity design and testing standpoint. The problem is now one of moisture diffusion through the bulk and package interfaces, which is different than water vapor permeating a crack in a glass to metal seal. A brief review of the techniques and methods to evaluate a "near-hermetic" approach is presented along with a discussion of the pitfalls and issues of TM 1014 (Seal) and TM 1018 (Internal Water Vapor) as applied to a “near hermetic package” along with the fundamental theory including: Fick’s law of moisture diffusion, WVTR, TGA and moisture diffusion coefficients. Applications of moisture sensing inside a package and a discussion on how to qualify a “near hermetic” package will be presented.

Who Should Attend?
This PDC is intended as an intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA results and for those responsible for evaluating new polymeric cavity style packages.

Thomas J. Green is the Principal at TJ Green Associates LLC, a Veteran owned small business devoted to providing world class teaching and consulting services in microelectronics packaging. As an independent consultant Tom's been responsible for numerous successful projects in the area of wirebond, die attach and package seal and associated leak test. As an Adjunct Professor at the National Training Center for Microelectronics he designs curriculum and teaches industry short courses relating to advanced microelectronics manufacturing processes. He has over twenty-five years of experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. Tom is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

Wire Bonding in Microelectronics (PDC8)
Course Leader: Lee Levine, Process Solutions Consulting

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many small- and large-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 25 µm ball bond pitch), and bonding to flex will be covered. Newer developments are included along with a major discussion of wire bonding to multichip substrates, soft substrates, Cu-Lok and the special intermetallic problems occurring when fine pitch chips are used. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds in general; cratering; cleaning for high yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of making very low loops, implementing TAB and Flip Chip by using wire bonding/stud bumping techniques.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Lee Levine is a consultant for Process Solutions Consulting where he provides process engineering consultation and SEM/EDS analysis. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 50 technical papers, and in 1999 won the John A. Wagnon Technical Achievement award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow, V.P of the Keystone Chapter, and V.P Technology for IMAPS. In addition he is a senior member of IEEE. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

Break: 3:00 pm – 3:20 pm

Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 7:00 pm

Device Packaging Advance Program
Register On-Line

 


Corporate
Sponsor:


Corporate Sponsor - NEXX Systems


Student Paper Competition
Sponsor:


Student Paper Competition Sponsor - The Microelectronics Foundation


Media
Sponsor:

3D InCites - Media Sponsor

Wafer & Device Packaging and Interconnect - Media Sponsor




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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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