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7th International Conference and Exhibition on
Device Packaging

www.imaps.org/devicepackaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA



Conference and Technical Workshops
March 8-10, 2011
Exhibition and Technology Showcase
March 8-9, 2011
Professional Development Courses
March 7, 2011
GBC Spring Conference
March 6-7, 2011

In conjunction with the Global Business Council (GBC) Spring Conference, March 6-7


Courtesy of Rensselaer Polytechnic Institute

Courtesy of US Army RDEDCOM AMRDEC

General Chair:

Phil Garrou
Microelectronic Consultants of NC


3D Packaging
Topical Workshop
Flip Chip Technologies
Topical Workshop
Wafer Level Packaging
Topical Workshop
MEMS & Microsystems
Topical Workshop
Emerging Tech (LEDs & Passives)
Topical Workshop
Technical Co-Chair:
Paul Siblerud
Applied Materials
Technical Co-Chair:
Peter Elenius
E&G Technology Partners
Technical Co-Chair:
Ted Tessier
FlipChip International
Technical Co-Chair:
Robert Dean
Auburn University
Technical Co-Chair:
Jeff Perkins
Yole
Technical Co-Chair:
Ron Huemoeller
Amkor Technology
Technical Co-Chair:
Alan Huffman
RTI International
Technical Co-Chair:
Rey Alvarado
Maxim Integrated Prod.
Technical Co-Chair:
Tracy Hudson
US Army
Technical Co-Chair:
Robert Heistand
AVX

EARLY REGISTRATION/EXHIBIT CUT-OFF: FEBRUARY 3, 2011
HOTEL DEADLINE: FEBRUARY 3, 2011

Device Packaging Program
Register On-Line | Hotel Information


Professional Development Courses (PDCs)

For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 7th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 7:00pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm. All are invited to register for this fun, new event which benefits the IMAPS Microelectronics Foundation.

PDC1: 3D Integration: Technology, Applications & Markets for 3D Integrated Circuits
PDC2: Guide to Component Chip Attach - Including Flip Chip
PDC3: MEMS Reliability and Packaging
PDC4: Fundamentals of Microelectronic Packaging
PDC5: Introduction to MEMS Design and Fabrication
PDC6: Polymers in Semiconductor Packaging
PDC7: Hermetic Sealing and Testing of Small Volume MEMS Packages

PDC8: Area Array Microelectronics Package Reliability

Morning Professional Development Courses
8:00 am – Noon
Monday, March 7

3D Integration: Technology, Applications & Markets for 3D Integrated Circuits (PDC1)
Course Leader: Philip Garrou, Microelectronic Consultants of NC

Course Description:
This course is based on the authors activity over the past 7 years with numerous companies in the industry, his weekly 3D blog “Insights From the Leading Edge “ in Solid State Technology and the 2nd volume Wiley-VCH book “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits” which he authored. The course will begin by defining and contrasting 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning, stacking and wire bonding to the BGA base). The various drivers for 3D integration including the electrical performance and economic issues will be examined. We will examine the various process sequences being proposed for 3D integration and the process unit operations necessary to fabricate a 3D stack. The process sequences proposed by IDMs, Universities, and Institutes will be compared and contrasted. We will then examine applications and the evolving infrastructure that will be necessary to accomplish this. The course will end by looking at the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.

Who Should Attend?
The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain.

Dr. Garrou consults in the areas of 3D IC integration, thin film technology, IC packaging and microelectronic materials. Dr. Garrou is a fellow of IEEE & IMAPS and was President of the IEEE CPMT (2003-2005) and IMAPS (1998). He is currently a contributing editor and weekly 3D IC blogger for Solid state Technology magazine “Insights From the Leading Edge”. Dr Garrou is a Sr. Analyst and contributor for the Yole Developpment “i-Micronews” and Yole newsletters. He has authored / co-authored > 100 technical publications and book chapters. He edited and authored the 2008 “Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits” for Wiley-VCH.

Guide to Component Chip Attach - Including Flip Chip (PDC2)
Course Leader: Phillip Creter, Creter & Associates

Course Description:
This course provides a training guide to successful component chip attach based on industry proven methods with details of materials, processes and equipment used in traditional component chip attachment of passives (capacitors, inductors, resistors), and actives (various silicon die including flip chips). Core chip attachment processes and details are grouped as follows: polymer, silver-glass frit, eutectic, SMT solder and polymer, sintered nanosilver and flip chip. Examples of actual process procedures and industry lot travelers are included. Special attention will be given to Flip Chip and Flip Chip packaging applications. Students will learn definitions, techniques, processes, materials, substrates and equipment used in flip chip attachment and underfill using both solder and polymers. Included: types of wafer bumping, pick/place, solder reflow, underfilling, and process control methodology. Reliability testing and screening methods as well as analysis techniques for various types of component attach are discussed using optical, die shear, scanning electron microscopy and scanning acoustic microscopy. Recommendations are made based on lessons learned, avoiding common pitfalls and tips how to solve problem areas. Figures, photos, video clips and actual pass around microcircuit samples enhance the learning experience. The class handout includes a glossary and an extensive list of over a hundred technical references.

Who Should Attend?
Engineers new to the field or those needing a running start in chip attach/flip chip packaging technology. No prior knowledge required.

Phillip Creter has over 30 years of microelectronics packaging experience. He is a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (received the highest GTE Corporate Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given numerous technical presentations, and has chaired many technical sessions for symposia. He has been teaching college level microelectronics since 1997 and has continuously taught courses at various symposia, workshops, and online microelectronics webinars. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of IMAPS and was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).

MEMS Reliability and Packaging (PDC3)
Course Leader: Slobodan Petrovic, Oregon Institute of Technology

Course Description:
The intended outcome of the course is to provide a comprehensive overview of the MEMS packaging and reliability principles; with a particular emphasis on sensors and actuators used in industrial, medical, and automotive applications. Examples of these applications include accelerometers, pressure sensors, angular rate sensors, micropumps, valves, and thermal inkjet heads. The packaging discussion will also cover a wide range of other MEMS principles and devices such biological and chemical sensors, optical imaging and displays, as well as photonic applications used in the fiber-optics industry. These applications will be illustrated using examples such as lab-on-a-chip, DNA sensor, radiation imager, micromirror device, tunable laser, and wavelength locker. Three extensive case studies that will be used to most effectively demonstrate diverse packaging principles are: accelerometers, pressure sensors, and digital micromirror devices.

Who Should Attend?
This is a survey course structured in such a way to provide a comprehensive overview of a broad array of packaging and reliability issues. While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will require a fairly detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field.

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, Oregon. Prior to that he was an associate professor at Arizona State University, where he was teaching courses in MEMS, Sensors, and alternative energy. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and nanocatalysts for energy applications. Prior to joining ASU Dr. Petrovic held appointments at Clear Edge Power (formerly Quantum Leap Technology) as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; industrial electrochemical processes; and catalysis. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

Fundamentals of Microelectronic Packaging (PDC4)
Course Leader: Casey Krawiec, Consultant

Course Description:
This course provides the fundamentals of microelectronic packaging to entry-level engineers, technicians, and others involved in manufacturing, purchasing, processing, R&D, quality, sales, and marketing. No prior knowledge of microelectronics is required. This course will provide the student with an overview of the history of microelectronics, core terminology and concepts, and the critical functions of electronic packaging. Students will learn the basic types of microelectronic packaging from a materials perspective. Regarding materials and package technology selection, students will gain an appreciation of the trade-offs between cost, performance, and reliability. The course will provide an overview on package assembly and test, and will conclude by reviewing the future/emerging technologies of packaging.

What Will Be Learned?
At the conclusion of this course, the student will: Be familiar with Microelectronic Packaging terminology; Know the function and purpose of Microelectronic Packaging; Understand the conditions that drive package selection (performance, cost, reliability); Understand the conditions that determine the materials used in the package construction; and Understand why so many packages are custom designs.

Casey Krawiec has been deeply involved with microelectronics and packaging for over 15 years. Most recently, he was Vice President of North American Sales at StratEdge Corporation, a packaging OEM and assembler in San Diego. Prior to that, he worked for Kyocera America, including a stint as the Offshore (International) Sales Manager. He began his career as a design engineer for the Department of the Navy. He has an MBA from the University of Louisville and a BS in Mechanical Engineering from the University of Kentucky. He is an officer in the local chapters of both International Microelectronics And Packaging Society and the American Society of Mechanical Engineers. He is married with three children and lives in La Jolla, California.

Break: 10:00 am – 10:20 am


Afternoon Professional Development Courses
1:00 pm – 5:00 pm

Introduction to MEMS Design and Fabrication (PDC5)
Course Leader: Philip J. Reiner, CGI Federal

Course Description:
This course provides a comprehensive overview of the design and fabrication of Micro-electrical and Mechanical Machine Systems (MEMS). The fundamentals of good MEMS design will be presented with numerous examples illustrating how to go about designing a MEMS device and the processing steps that lead to a functioning part. Discussions will include in-depth descriptions of various microlithography processing equipment such as reactive ion etchers, coaters, spinners, mask aligners, pattern generators, dicing equipment, etc. The student will also learn the basics of microlithography wafer processing, bonding, and finishing processes such as dicing and packaging. The student will be taken through a typical MEMS design problem step by step from concept to finished product. At the end of the course, the student will have a firm grasp of the tools and techniques available for fabricating MEMS devices and the knowledge required to make sensible choices in process design and product flow.

Who Should Attend?
This course is offered at the introductory level for anyone interested in getting into MEMS design and fabrication.

Dr. Philip J. Reiner is the Chief Scientist for the Advanced Engineering Technology Division for Stanley Associates Inc. in Huntsville, Alabama. His group provides full spectrum design, development, and fabrication support services for systems based on MEMS/NEMS, fiber optic, and electro-optic technologies. He holds a BS in Physics from RIT and a PhD in Physics from the University of Rochester in New York. His research interests include Nano-technologies, MicroElectroMechanical Systems (MEMS) development, Liquid Crystal Polymers, and Thin and Thick Film Technologies development. Dr. Reiner is currently developing advanced MEMS-based components and systems for commercial and defense applications. He also develops advanced research programs for multiple US agencies. He is a member of IEEE, ISA, and NDIA and currently holds five patents. He also served as a Captain in the US Army Ordnance Corp. and was awarded the Meritorious Service Medal in 1989.

Polymers in Semiconductor Packaging (PDC6)
Course Leader: Jeffrey Gotro, InnoCentrix, LLC

Course Description:
This course will provide a broad overview of polymers and the important structure-property-process-performance relationships for electronic packaging. Topics to be covered are thermosetting polymers versus thermoplastics, thermosetting polymer curing, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts). The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), capillary underfills, packaging substrate materials, encapsulants (mold compounds), and coatings. In most cases, adhesives, underfills, mold compounds and coatings are applied as a viscous liquid and then cured. The flow properties are critical to performance in high volume manufacturing. The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, rheology changes during curing), underfills, and mold compounds.

Who Should Attend?
Packaging engineers and R&D professionals involved in the development, production, and reliability testing of semiconductor packages would benefit from the course.

Dr. Jeffrey Gotro has over twenty-six years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He is an accomplished technology professional with demonstrated success solving complex polymer problems, directing new product development, and enabling clients to improve the financial impact of their polymer technologies. Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. Jeff is a nationally recognized authority in thermosetting polymers and he has received invitations to present lectures and short courses at national technical conferences. He has published 60 technical papers (including 4 book chapters) in the field of polymeric materials for advanced electronic packaging applications, holds 13 issued US patents, and has 8 patents pending. Jeff has a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science and a B.S. in Mechanical Engineering/Materials Science from Marquette University.

Hermetic Sealing and Testing of Small Volume MEMS Packages (PDC7)
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
Reliable packaging of MEMS requires the ability to create and maintain a suitable inert atmosphere or vacuum inside the package cavity for the expected lifetime of the device. Traditional hermetic ceramic/metal packages are being replaced by wafer level packaging techniques, which present unique challenges from a hermeticity testing perspective. This course begins with an overview of traditional hermetic sealing processes along with wafer level MEMS packaging processes and methods. In some cases near-hermetic packages, such as LCP are suitable in some applications. Testing of small cavity MEMS packages according to the traditional Mil Spec TM 1014 requirements may not be sufficient to guarantee reliable operation. Difficulties and limitations in fine leak testing of small volume packages will be addressed. Recent advances in Optical Leak Testing (OLT), Cumulative Helium Leak Detection (CHLD) along with other hermeticity techniques are reviewed in light of the new, tighter leak rate hermeticity specifications. Moisture ingress is of primary concern for a small volume MEMS cavity packages. Moisture level vs. surface area to volume ratio is an important concept, along with material outgassing and the potential to mitigate these problems with getters. These along with other critical MEMS packaging issues are addressed in this PDC.

Who Should Attend?
This PDC is intended as an introductory level course for process engineers, designers, quality engineers, and managers responsible for packaging and hermetic testing of cavity style MEMS..

Thomas J. Green is an independent consultant and respected teacher. Tom is the principal at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business specializing in teaching and consulting for the microelectronics industry. Tom previously worked at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified hybrid microcircuits for military satellites. Tom has demonstrated expertise in seam sealing and hermeticity leak testing processes. He has conducted numerous hermeticity experiments and presented many technical papers and co-authored the latest release of MIL-STD-883 TM 1014 (Seal). Tom is an active IMAPS member and Society Fellow and has worked as a hermeticity consultant for a variety military and medical companies. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

Area Array Microelectronics Package Reliability (PDC8)
Course Leader: Amaneh Tasooji, Arizona State University

Course Description:
The objective of this workshop is to provide an overview on area array package reliability analysis and tools, and bestow awareness on critical factors impacting microelectronics packaging integrity. Area Array microelectronic packages with small pitch and large I/O count grid array are used in commercial and military applications. Reliability and risk assessment analysis of these widely used packages is critical element of product design and field support. Current practice in reliability focuses on accelerated-testing of manufactured components (representing the factory and OEM assembly, shipping and storage, on/off environment, and user interface) and monitors the component failure under these conditions. Acceleration Factor (AF) is determined using the accelerated test data, and the performance/reliability of the package under “use condition” is then predicted. Statistical methods and Life prediction methodologies are used in conjunction with local/global elastic- and/or inelastic-stress/strain analysis for component reliability assessment. This workshop briefly reviews area array design and discusses reliability approach, focusing on solder joints and reviewing the impact of various parameters (e.g., materials, design, and processing parameters) on joint reliability. Deformation and failure mechanisms (e.g., creep and fatigue) influencing reliability of solder joints are discussed in detail.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with area array packages and general device assembly technologies.

Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering and manufacturing. She received her Ph. D. in Materials Science and Engineering from Stanford University in 1982 and has B. S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, component design, manufacturing, and quality/reliability in many industries such as microelectronics, aerospace, and nuclear. She has had many technical and leadership responsibilities while at Honeywell/AlliedSignal and has developed many materials behavior, deformation, and fracture models for reliability analysis. Dr. Tasooji was the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. Dr. Tasooji has developed and delivered many graduate engineering courses (e.g., Introduction to Micro-electronic Packaging, Overview of Materials Science and Engineering for Microelectronics Packaging, Advanced Packaging Analysis and Design: Material Considerations, Nuclear Materials) and many undergraduate courses at Arizona State University (ASU). She has leveraged new technology and e-learning concepts in developing and offering conventional (face-to-face) and hybrid courses (on-campus and distance training) at ASU, emphasizing Interactive Learning concept, and providing professionals with tools/opportunity for continuous learning.

Break: 3:00 pm – 3:20 pm

Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 7:00 pm

Microelectronics Foundation Ca-Si-No Night (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm


Device Packaging Program
Register On-Line

 


Exhibit Hall Reception
Sponsor:


Exhibit Hall Reception Sponsor: Williams Advanced Materials

GBC Speaker Dinner & Foundation Golf/Hold'em Sponsors:

Premier "Eagle" Sponsor: ASE US, Inc.


Premier "Birdie" Sponsor: Amkor Technology


Student Paper Competition
Sponsor:


Student Paper Competition Sponsor - The Microelectronics Foundation


Golf Hole Sponsors:

Golf Hole Sponsor: Teledyne Microelectronics

Golf Hole Sponsor: AGC Electronics America

Golf Hole Sponsor: Coining Inc/SPM

Golf Hole Sponsor: Kyzen Corp.

Golf Hole Sponsor: ASE US, Inc.

Golf Hole Sponsor: Amkor Technology

Golf Hole Sponsor: LORD Corporation

Media Sponsors:

I-Micronews

MEPTEC




© Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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