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8th International Conference and Exhibition on
Device Packaging

www.imaps.org/devicepackaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA



Conference and Technical Workshops
March 6-8, 2012
Exhibition and Technology Showcase
March 6-7, 2012
Professional Development Courses
March 5, 2012
GBC Spring Conference
March 4-5, 2012

In conjunction with the Global Business Council (GBC) Spring Conference, March 4-5


Courtesy of Rensselaer Polytechnic Institute

Courtesy of US Army RDEDCOM AMRDEC


General Chair:

Peter Elenius
E&G Technology Partners

General Chair-elect (PDCs):
James Lu
Rensselaer Polytechnic Institute
Past General Chair (Panels):
Phil Garrou
Microelectronic Consultants of NC


3D & 2.5D Packaging
Topical Workshop
Flip Chip & Wafer Level Packaging
Topical Workshop
MEMS & Microsystems
Topical Workshop
Passive Integration
Topical Workshop
LED Packaging
Topical Workshop
Technical Co-Chair:
Ron Huemoeller
Amkor Technology
Technical Co-Chair:
Rey Alvarado
Maxim Integrated Prod.
Technical Co-Chair:
Robert Dean
Auburn University
Technical Co-Chair:
Franck Murray
IPDIA
Technical Co-Chair:
Thomas Goodman
E&G Technology Partners
Technical Co-Chair:
Rozalia Beica
Lam Research AG
Technical Co-Chair:
Alan Huffman
RTI International
Technical Co-Chair:
Tracy Hudson
US Army
Technical Co-Chair:
Kai Liu
STATS ChipPAC
Technical Co-Chair:
Bob Karlicek
Rensselaer Polytechnic Institute

EARLY REGISTRATION/EXHIBIT/Hotel Deadlines: February 10, 2012


Technical Program | Download Program PDF
Exhibition Details | Reserve Exhibits On-line | Floorplan | 2012 Exhibitors | 2011 Exhibitors
Global Business Council (GBC) Spring Conference
Spring Golf Invitational | Texas Hold'em Tournament


Professional Development Courses (PDCs)

For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 5th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 6:30pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm. All are invited to register for this fun, new event which benefits the IMAPS Microelectronics Foundation.

When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2.

7:00 am - 7:00 pm
Registration
7:00 am - 8:00 am
Continental Breakfast
8:00 am - 12:00 pm
Morning Professional Development Courses (PDCs)
PDC1: Polymers for Electronic Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
PDC2: Mechanical Design and Reliability Analysis in Microelectronics Packaging
Course Leader: Amaneh Tasooji, Arizona State University
PDC3: 3D Integration: Technology, Applications & Markets for 3D Integrated Circuits
Course Leader: Philip Garrou, Microelectronic Consultants of NC
PDC4: Basics of Microelectronic Packaging
Course Leader: Casey Krawiec, Gel-Pak/Quik-Pak
PDC5: Introduction to MEMS Design and Fabrication
Course Leader: Philip J. Reiner, CGI Federal
CANCELLED
10:00 am - 10:20 am
Break
12:00 pm - 1:00 pm
Lunch Only provided for those attendees registered for both Morning and Afternoon PDCs
1:00 pm - 5:00 pm
Afternoon Professional Development Courses (PDCs)
PDC6: Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, NDSU - CNSE
PDC7: Wire Bonding in Microelectronics
Course Leader: Lee Levine, Process Solutions Consulting, Inc.
PDC8: Hermetic Sealing and Testing of Small Volume MEMS Packages
Course Leader: Thomas J. Green, TJ Green Associates LLC
PDC9: 2.5 and 3D Interposer Technologies and Applications
Course Leader: Venky Sundaram, Georgia Institute of Technology (PRC)
PDC10: Packaging of High Brightness Light-Emitting Diodes for Solid-State Lighting
Course Leader: Sheng Liu, Huazhong University of Science and Technology
CANCELLED
3:00 pm - 3:20 pm
Break
5:00 pm - 6:30 pm
Welcome Reception (All Attendees "GBC & DPC" Are Invited To Attend)
7:00 pm - 10:00 pm
Texas Hold'em Tournament (Limited Seating)
To Benefit the IMAPS Microelectronics Foundation


Morning Professional Development Courses
8:00 am - Noon
Monday, March 5

PDC1: Polymers for Electronic Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC

Course Description:
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be: 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application, 3) learn the fundamentals of polymer characterization related to electronic packaging, 4) develop a foundation in rheology and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this series valuable.

Dr. Jeffrey Gotro has over twenty-six years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He is an accomplished technology professional with demonstrated success solving complex polymer problems, directing new product development, and enabling clients to improve the financial impact of their polymer technologies. Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. Jeff is a nationally recognized authority in thermosetting polymers and he has received invitations to present lectures and short courses at national technical conferences. He has published 60 technical papers (including 4 book chapters) in the field of polymeric materials for advanced electronic packaging applications, holds 13 issued US patents, and has 8 patents pending. Jeff has a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science and a B.S. in Mechanical Engineering/Materials Science from Marquette University.

PDC2: Mechanical Design and Reliability Analysis in Microelectronics Packaging
Course Leader: Amaneh Tasooji, Arizona State University

Course Description:
The objective of this workshop is to provide an overview of mechanical design and discuss the reliability analysis and tools used in microelectronics packaging. Mechanical design requirements and analysis approaches are reviewed, and Traditional/Classical and Damage-Tolerant (Fracture-Mechanics and LEFM) approaches are discussed. Stress-strain response (including thermal loading due to CTE-mismatch), materials behavior and constitutive models, and failure mechanisms (brittle/ductile fracture, DBTT, creep, and fatigue) are reviewed. Closed form solutions and analytical approaches (FEM, Finite Element Methods) are presented. Mechanical metrologies such as Moire used in measuring package deformation (e.g., warpage) and validating analytical FEM results are reviewed. Reliability analysis and tools used in ensuring mechanical integrity are discussed. Methodology used in determining acceleration factor (AF) for predicting package performance/reliability under "use condition" is presented. Statistical methods and Life prediction methodologies used in mechanical analysis and component reliability assessment are discussed.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with microelectronics packaging and general device assembly technologies.

Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering and manufacturing. She received her Ph.D. in Materials Science and Engineering from Stanford University in 1982 and has a B. S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, component design, manufacturing, and quality/reliability in many industries such as microelectronics, aerospace, and nuclear. Dr. Tasooji was the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. Dr. Tasooji has developed and delivered many graduate and undergraduate engineering courses (e.g., "Introduction to Micro-electronic Packaging," "Overview of Materials Science and Engineering for Microelectronics Packaging," "Advanced Packaging Analysis and Design: Material Considerations," "Nuclear Materials," etc.) at Arizona State University (ASU). She has leveraged new technology and e-learning concepts in developing and offering conventional (face-to-face) and hybrid courses (on-campus and distance training) at ASU.

PDC3: 3D Integration: Technology, Applications & Markets for 3D Integrated Circuits
Course Leader: Philip Garrou, Microelectronic Consultants of NC

Course Description:
This course is based on the author's activity over the past 7 years with numerous companies in the industry, his weekly 3D blog "Insights From the Leading Edge " in Solid State Technology and the 2nd volume Wiley-VCH book "Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits" which he authored. The course will begin by defining and contrasting 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning, stacking and wire bonding to the BGA base). The various drivers for 3D integration including the electrical performance and economic issues will be examined. We will examine the various process sequences being proposed for 3D integration and the process unit operations necessary to fabricate a 3D stack. The process sequences proposed by IDMs, Universities, and Institutes will be compared and contrasted. We will then examine applications and the evolving infrastructure that will be necessary to accomplish this. The course will end by looking at the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.

Who Should Attend?
The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain.

Dr. Garrou consults in the areas of 3D IC integration, thin film technology, IC packaging and microelectronic materials. Dr. Garrou is a fellow of IEEE & IMAPS and was President of the IEEE CPMT (2003-2005) and IMAPS (1998). He is currently a contributing editor and weekly 3D IC blogger for Solid state Technology magazine "Insights From the Leading Edge." Dr Garrou is a Sr. Analyst and contributor for the Yole Developpment "i-Micronews" and Yole newsletters. He has authored / co-authored > 100 technical publications and book chapters. He edited and authored the 2008 "Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits" for Wiley-VCH.

PDC4: Basics of Microelectronic Packaging
Course Leader: Casey Krawiec, Gel-Pak/Quik-Pak

Course Description:
This course will provide the student with an overview of the history of microelectronics, core terminology and concepts, and the critical functions of microelectronic packaging. Students will learn the basic types of microelectronic packaging from a materials perspective. Regarding materials and packaging technology selection, students will gain an appreciation of the trade-offs between cost, performance, and reliability. The course will provide an overview on package assembly and test, and will conclude by reviewing the future/emerging packaging technologies.

Who Should Attend?
The course is for entry-level engineers, technicians, and others involved in manufacturing, purchasing, processing, R&D, quality, sales, and marketing.

Casey Krawiec has been deeply involved with microelectronics and packaging for over 15 years. Most recently, he was Vice President of North American Sales at StratEdge Corporation, a packaging OEM and assembler in San Diego. Prior to that, he worked for Kyocera America, including a stint as the Offshore (International) Sales Manager. He began his career as a design engineer for the Department of the Navy. He has an MBA from the University of Louisville and a BS in Mechanical Engineering from the University of Kentucky. He is an officer in the local chapters of both International Microelectronics And Packaging Society and the American Society of Mechanical Engineers.

PDC5: Introduction to MEMS Design and Fabrication
Course Leader: Philip J. Reiner, CGI Federal

PDC CANCELLED

Break: 10:00 am - 10:20 am


Afternoon Professional Development Courses
1:00 pm - 5:00 pm

PDC6: Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, NDSU - CNSE

Course Description:
The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by-step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and SMT and their solution will be outlined.

Who Should Attend?
Non-packaging personnel will learn ins and outs of chip packaging. It will help them understand the effects of package configurations on their work and the effect of their work on chip packages. Personnel entering the packaging field will have a critical look at the quality, reliability and materials issues related to the development and manufacture of chip packages. Non-technical personnel will learn the material and manufacturing intricacies of simple-looking chip packages.

Syed Sajid Ahmad contributed to quality and reliability enhancement of assembly processes at Intel (1979-89), especially wire bond. Ahmad contributed to packaging development at National Semiconductor (1990) and managed quality at GigaBit/TriQuint (1990-91). His major work at Micron Technology (1991-2003) involved materials enhancement resulting in high reliability products and the development and implementation of advanced packaging. At the Center for Nanoscale Science and Engineering (2003-present), his focus is on enhancing advanced packaging related research and manufacturing capabilities at the center in the areas of thin film, thick film, advanced packaging (CSP) and surface mount technology (SMT). Ahmad has 32 publications and presentations and holds 54 US patents.

PDC7: Wire Bonding in Microelectronics
Course Leader: Lee Levine, Process Solutions Consulting, Inc.

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many small- and large-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 25 um ball bond pitch), and bonding to flex will be covered. Newer developments are included along with a major discussion of wire bonding to multichip substrates, soft substrates, Cu-Lok and the special intermetallic problems occurring when fine pitch chips are used. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds in general; cratering; cleaning for high yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed; and the metallurgy of gold and aluminum wire. It concludes with methods of making very low loops, implementing TAB and Flip Chip by using wire bonding/stud bumping techniques.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Lee Levine's experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. Currently he consults for his own company, Process Solutions Consulting, Inc., providing process consulting yield improvement, SEM, EDS and Metallography services to the microelectronics industry. He has been awarded 4 patents, published more than 70 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics And Packaging Society, IMAPS. Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is an IMAPS Fellow and former IMAPS VP of Technology. Lee is also a Contributing Editor for Test and Packaging Times (www.taptimes.com), an online newsletter, where he publishes a column "Levine on Bonding." Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

PDC8: Hermetic Sealing and Testing of Small Volume MEMS Packages
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
Reliable packaging of MEMS requires the ability to create and maintain a suitable inert atmosphere or vacuum inside the package cavity for the expected lifetime of the device. Traditional hermetic ceramic/metal packages are being replaced by wafer level packaging techniques, which present unique challenges from a hermeticity testing perspective. This course begins with an overview of traditional hermetic sealing processes along with wafer level MEMS packaging processes and methods. In some cases near-hermetic packages, such as LCP are suitable for some applications. Testing of small cavity MEMS packages according to the traditional Mil Spec TM 1014 requirements may not be sufficient to guarantee reliable operation. Difficulties and limitations in fine leak testing of small volume packages will be addressed. Recent advances in Optical Leak Testing (OLT), Cumulative Helium Leak Detection (CHLD) and Radioisotope KR 85, along with other hermeticity techniques, such as pirani vacuum sensors, are reviewed in light of the hermeticity specifications. Gaseous ingress is of primary concern for small volume MEMS cavity packages. Moisture level vs. surface area to volume ratio is an important concept, along with material outgassing and the potential to mitigate these problems with getters. These along with other critical MEMS packaging issues are addressed.

Who Should Attend?
This PDC is intended as an introductory level course for process engineers, designers, quality engineers, and managers responsible for packaging and hermetic testing of cavity style MEMS.

Thomas J. Green is the principal at TJ Green Associates LLC (www.tjgreenllc.com), a veteran owned small business specializing in teaching and consulting for the microelectronics industry. Tom has demonstrated expertise in sealing and hermeticity testing of products intended for high rel military and medical applications. He is currently on the JEDEC committee helping to revise TM 1014 and has served as an expert witness in medical cases related to hermeticity failures. Tom is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters in Engineering.

PDC9: 2.5D and 3D Interposer Technologies and Applications
Course Leader: Venky Sundaram, Georgia Institute of Technology (PRC)

Course Description:
This course will present a comprehensive review of the latest 2.5D and 3D interposer approaches being developed worldwide. High density interposers are emerging as a mainstream technology for packaging of heterogeneous ICs and 3D ICs, but also as a simpler and better alternative to 3D ICs with TSV, eventually providing a path for integration of sub-systems or entire systems. Silicon and glass interposers are emerging as the front-runners to address the I/O, CTE, warpage and thermal limitations of current organic packages. The topics covered include Electrical & Mechanical Design, Silicon Interposers, Glass Interposers, Chip Level & Board Level Interconnections, Applications and Markets, and Manufacturing Infrastructure for interposers. Wafer based BEOL Si interposers as well as emerging panel based glass and other interposer technologies will be described in detail. A variety of materials and process options for interposer fabrication will be presented. The technical and business challenges that must be addressed for successful implementation of interposers in 3D packages will be discussed. Specific examples of key interposer developments such as Xilinx stacked silicon interconnect, MEMS packaging using glass interposers, silicon interposer for high performance CPU packaging, and logic-memory high bandwidth 3D integration will be highlighted.

Who Should Attend?
The course is a must-attend event for those highly interested in interposer technology advances for the future. The course is intended for a broad audience including semiconductor and packaging managers, technologists, engineers, industry and academic researchers, and students.

Dr. Venky Sundaram is Director of Research at the 3D Systems Packaging Research Center (PRC), Georgia Tech. He is Program Manager for the Silicon and Glass Interposer (SiGI) industry consortium with more than 20 active global industry members. His research expertise is in the areas of System on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components and systems integration research. He is a globally recognized expert in packaging technology and a co-founder of Jacket Micro Devices, an RF/wireless start-up acquired by AVX. Dr. Sundaram is the co-chairman of the IEEE CPMT Technical Committee on High Density Substrates and is on the Executive Council of IMAPS as Director of Education Programs. Dr. Sundaram has won several best paper awards and has 15+ patents and 100+ publications. He received his BS from IIT Mumbai, and MS and PhD in Materials Science and Engineering from Georgia Tech.

PDC10: Packaging of High Brightness Light-Emitting Diodes for Solid-State Lighting
Course Leader: Dr. Sheng Liu, Huazhong University of Science and Technology

PDC CANCELLED

Break: 3:00 pm - 3:20 pm

Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 6:30 pm

Microelectronics Foundation Texas Hold'Em Tournament (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm


Device Packaging Home

When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2.



DPC/GBC Premier Sponsors:

DPC/GBC Premier Sponsor: Solid State Equipment Corp.

DPC/GBC Premier Sponsor: ASE US, Inc.

DPC/GBC Premier Sponsor: Amkor Technology

Event Sponsor - Exhibit Reception, Lunch & Break:

Applied Materials - Event Sponsor

Post-Conference Presentations USB Drives:

ALLVIA - Event Sponsor

Coffee Break Sponsor:
Sikama - Coffee Break Sponsor

Student Paper Competition
Sponsor:


Student Paper Competition Sponsor - The Microelectronics Foundation

Golf Hole Sponsors:

DPC/GBC Premier Sponsor: Solid State Equipment Corp.

DPC/GBC Premier Sponsor: ASE US, Inc.

Golf Hole Sponsor: Amkor Technology

Hole Sponsor: NAMICS

Golf Hole Sponsor: LORD Corporation

Golf Hole Sponsor: Coining Inc/SPM

Golf Hole Sponsor: AGC Electronics America

Golf Hole Sponsor: Kyzen Corp.

Media Sponsors:

MEPTEC

Yole Developpement

I-Micronews

3D InCites - Media Sponsor



© Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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