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9th International Conference and Exhibition on
Device Packaging

www.imaps.org/devicepackaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA



Conference and Technical Workshops
March 12-14, 2013
Exhibition and Technology Showcase
March 12-13, 2013
Professional Development Courses
March 11, 2013
GBC Spring Conference
March 10-11, 2013

In conjunction with the Global Business Council (GBC) Spring Conference, March 10-11


Courtesy of Rensselaer Polytechnic Institute

Courtesy of US Army RDEDCOM AMRDEC


General Chair:

James Lu
Rensselaer Polytechnic Institute

General Chair-elect (PDCs):
Ron Huemoeller
Amkor Technology
Past General Chair (Panels):
Peter Elenius
E&G Technology Partners

3D & 2.5D Packaging
Topical Workshop
Flip Chip & Wafer Level Packaging
Topical Workshop
MEMS & Microsystems
Topical Workshop
LED Packaging for SSL
Topical Workshop
Technical Chair:
Rozalia Beica
Lam Research AG
Technical Chair:
Linda Bal
Freescale Semiconductor
Technical Chair:
Tracy Hudson
US Army
Technical Chair:
Thomas Goodman
E&G Technology Partners
Technical Co-Chair:
Peter Ramm
Fraunhofer EMFT
Technical Co-Chair:
Luu Nguyen
Texas Instruments
Technical Co-Chair:
Russell Shumway
Amkor Technology
Technical Co-Chair:
Bob Karlicek
Rensselaer Polytechnic Institute


EARLY REGISTRATION/EXHIBIT/Hotel Deadlines: February 8, 2013


Register On-Line

Technical Program | Download Program PDF
Exhibition Details | Floorplan | 2013 Exhibitors | 2012 Exhibitors
Global Business Council (GBC) Spring Conference
Spring Golf Invitational | Texas Hold'em Tournament


Professional Development Courses (PDCs)

For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 11th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 6:30pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm (TBD). All are invited to register for this fun, new event which benefits the IMAPS Microelectronics Foundation.

When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact bschieman@imaps.org with questions..

7:00 am - 7:00 pm
Registration
7:00 am - 8:00 am
Continental Breakfast
8:00 am - 12:00 pm
Morning Professional Development Courses (PDCs)
PDC1: 2.5D/3D, Flip Chip WLP, MEMS & LED Packaging Trends, Updates & Advances
Course Leader: Phil Creter, Creter & Associates
PDC2: Recent Advances in Glass and Silicon Interposers for 2.5D and 3D Integration
Course Leader: Venky Sundaram, Georgia Institute of Technology (PRC)
PDC3: High-Temperature Electronics - with an Emphasis on Assembly & Packaging
Course has been cancelled
PDC4: Hermetic Sealing and Testing of Small Volume MEMS Packages
Course Leader: Thomas J. Green, TJ Green Associates LLC
PDC5: Failure Mode Analysis of Flip Chip and Advanced Package and Board Assemblies
Course Leader: Daniel Baldwin, Engent Inc.
10:00 am - 10:20 am
Break
12:00 pm - 1:00 pm
Lunch Only provided for those attendees registered for both Morning and Afternoon PDCs
1:00 pm - 5:00 pm
Afternoon Professional Development Courses (PDCs)
PDC6: Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging
Course Leaders: TJ Kiczenski, Aric Shorey, Corning, Inc.
PDC7: Polymers in Semiconductor Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
PDC8: Thermal and Mechanical Simulation Techniques - An Introductory Course for 3D Enablement Professionals
Course Leader: Kamal Karimanal, Cielution LLC
PDC9: MEMS Reliability and Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
PDC10: Basics of Conventional and Advanced Packaging
Course Leader: Syed Sajid Ahmad, NDSU - CNSE
3:00 pm - 3:20 pm
Break
5:00 pm - 6:30 pm
Welcome Reception (All Attendees "GBC & DPC" Are Invited To Attend)
7:00 pm - 10:00 pm
Texas Hold'em Tournament (Limited Seating)
To Benefit the IMAPS Microelectronics Foundation


Morning Professional Development Courses
8:00 am - Noon
Monday, March 11

PDC1: 2.5D/3D, Flip Chip WLP, MEMS & LED Packaging Trends, Updates & Advances
Course Leader: Phillip G. Creter, Creter & Associates

Course Description:
This NEW overview focuses on the four technical topics of this 2013 Device Packaging Conference, independently reviewing leading edge technical developments featuring the latest in microelectronics updates/trends.

Specific topics from 2012-1Q2013 conferences, technical papers, news reports:

- 2.5D/3D (Status/market, wide I/O memory stacking, polymer isolated TSVs, silicon bridge TSVs, fusion glass substrates, wafer adhesives, thin stacking, test vehicle demos, self-assembly).
-
Flip Chip Wafer Level Packaging (Status/market, fine pitch copper pillars, electromigration, intermetallic compound studies, non-conductive film used in wafer level underfill, low cost FC-PoP, electromigration of lead free solder bumps).
- MEMS (Status/market, challenges, novel approaches, hermetic wafer level packaging, drop reliability, flex adhesive).
- LED Packaging (Status/market, high power heat sinks/die attach material, novel encapsulants, silicon/glass/GaN substrates).

Technical innovations related to the above topics presented with input from leading industrial/academic institutions: Advanced Semiconductor Engineering/ASE, Altera, Amkor, CEA-Leti, Corning, DELO, Georgia Institute of Technology, Global Foundries, Hitachi, Hong Kong University, IBM, IFTLE, Intel, ITRS, Karlsruhe Institute, Microsystems, NAMICS, National Tsing Hua University, Oracle, Philips Lumileds, Qualcomm, Samsung, Sandia National Labs, Sematech, Solid State Technology, Siliconware Precision Industries/SPIL, TechSearch, Tohoku University, Toray, Toshiba, University of California, Wuhan National Laboratory for Optoelectronics, Xilinx, Yole and others.

Emphasis on visual aids (photos, figures, videos) with pass-around microcircuit samples. An invaluable handout includes over 100 references.

Who Should Attend?
Designed primarily for all engineers, scientists and others interested in an up-to-date overview of new developments in 3D, Flip Chip, MEMS and LED. The course uses simple terms and many graphics and figures to describe these elements of advanced packaging for those who are new to the field and needing a running start in these four focused areas of packaging technology. Ideal for entry-level technicians and engineers but also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management since it also includes a short review of current single chip and advanced wafer levels of 3D packaging.

Phillip Creter is a consultant (Creter & Associates) with 30 years of microelectronics experience at Polymer Flip Chip, Mini-Systems, GTE, Itek Corporation. Past positions at GTE included Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), and Principal Investigator of GTE IR&D Projects. Other positions elsewhere included management in Projects/Process Engineering, Process Development, Materials Engineering/Manufacturing Engineer, receiving many awards of distinction. Creter has been teaching college-level microelectronics courses since 1997. He has continuously taught PDCs since 2004 for online webinars and national microelectronics symposia/workshops. He is a well-known presenter having published technical papers in IEEE Transactions, Solid State Technology, High Density Interconnect, Circuits Manufacturing, Insulation Circuits, others. He has chaired many technical symposia sessions, given numerous technical presentations, is a US patent-holder. He is an active certified Department of Homeland Security instructor, a Life member of IMAPS, elected Fellow of the Society, and has held several executive committee offices both locally/nationally.

PDC2: Recent Advances in Glass and Silicon Interposers for 2.5D and 3D Integration
Course Leader: Venky Sundaram, Georgia Institute of Technology (PRC)

Course Description:
This course will present a comprehensive review of the latest 2.5D and 3D interposer approaches being developed worldwide. High density interposers are emerging as a mainstream technology for packaging of heterogeneous ICs and 3D ICs, but also as a simpler and better alternative to 3D ICs with TSV, eventually providing a path for integration of sub-systems or entire systems. Silicon and glass interposers are emerging as the front-runners to address the I/O, CTE, warpage and thermal limitations of current organic packages. The topics covered include Electrical & Mechanical Design, Silicon Interposers, Glass Interposers, Chip Level & Board Level Interconnections, Applications and Markets, and Manufacturing Infrastructure for interposers. Wafer based BEOL Si interposers as well as emerging panel based glass and other interposer technologies will be described in detail. A variety of materials and process options for interposer fabrication will be presented. The technical and business challenges that must be addressed for successful implementation of interposers in 3D packages will be discussed. Specific examples of key interposer developments such as Xilinx stacked silicon interconnect, MEMS packaging using glass interposers, silicon interposer for high performance CPU packaging, and logic-memory high bandwidth 3D integration will be highlighted. For 2013, the course materials will be updated to include technology highlights in the past twelve months.

Who Should Attend?
This popular course is a must-attend event for those highly interested in interposer technology advances for the future. The course is intended for a broad audience including semiconductor and packaging managers, technologists, engineers, industry and academic researchers, and students.

Dr. Venky Sundaram is the Director of Research at the 3D Systems Packaging Research Center (PRC), Georgia Tech. He is the Program Manager for the Silicon and Glass Interposer (SiGI) industry consortium with more than 25 active global industry members. His research expertise is in the areas of System on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components and systems integration. He is a globally recognized expert in packaging technology and a co-founder of Jacket Micro Devices, an RF/wireless start-up acquired by AVX. Dr. Sundaram is the co-chairman of the IEEE CPMT Technical Committee on Interconnections and Substrates and is on the Executive Council of IMAPS as Director of Education Programs. Dr. Sundaram has won several best paper awards and has 15+ patents and 100+ publications. He received his BS from IIT Mumbai, and MS and PhD in Materials Science and Engineering from Georgia Tech.

PDC3: High-Temperature Electronics - with an Emphasis on Assembly & Packaging
Course Leader: Randall Kirschman, Consultant

COURSE HAS BEEN CANCELLED

PDC4: Hermetic Sealing and Testing of Small Volume MEMS Packages
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
Reliable packaging of MEMS requires the ability to create and maintain a suitable inert atmosphere or vacuum inside the package cavity for the expected lifetime of the device. Traditional hermetic ceramic/metal packages are being replaced by wafer level packaging techniques, which present unique challenges from a hermeticity testing perspective. This course begins with an overview of traditional hermetic sealing processes along with wafer level MEMS packaging processes and methods. In some cases near-hermetic packages, such as LCP are suitable for some applications. Testing of small cavity MEMS packages according to the traditional Mil Spec TM 1014 requirements may not be sufficient to guarantee reliable operation. Difficulties and limitations in fine leak testing of small volume packages will be addressed. Recent advances in Optical Leak Testing (OLT), Cumulative Helium Leak Detection (CHLD) along with other hermeticity techniques, such as pirani vacuum sensors, are reviewed in light of the new tighter hermeticity specifications. Gaseous ingress is of primary concern for a small volume MEMS cavity packages. Moisture level vs. surface area to volume ratio is an important concept, along with material outgassing and the potential to mitigate these problems with getters. These along with other critical MEMS packaging issues are addressed.

Who Should Attend?
This PDC is intended as an intermediate level course for process engineers, designers, quality engineers, and managers responsible for packaging and hermetic testing of small volume cavity style packages.

Thomas J. Green is the principal at TJ Green Associates LLC (www.tjgreenllc.com), a veteran owned small business specializing in teaching and consulting for the microelectronics industry. Tom has demonstrated expertise in sealing and hermeticity testing of products intended for high rel military and medical applications. He is currently on the JEDEC committee helping to revise TM 1014 and has served as an expert witness in medical cases related to hermeticity failures. Tom is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters in Engineering.

PDC5: Failure Mode Analysis of Flip Chip and Advanced Package and Board Assemblies
Course Leader: Daniel Baldwin, Engent, Inc.

Course Description:
Over the past few years, numerous advanced packaging and process technologies have emerged such as flip chip in package, PoP, SiP, WLCSP, 3D-WLCSP, QFN, etc.. While a large number of technical publications are available to help with process requirements, understanding failure modes and reliability standards is essential for these technologies to be successfully sustained in production. This course will present reliability test procedures, assembly process defects, and common failure modes that occur in advanced package and board level assemblies. It will focus on process defect identification and resolution, failure mechanisms and the associated analysis tools needed to identify them such as FTIR, XRF, transmission X-ray analysis, acoustic microscopy and scanning electron microscopy. Numerous process defects and failure modes will be presented along with extensive visual aids to provide a more intuitive understanding of the defects and failure modes associated with these advanced assemblies. It will also discuss artifacts leading to process defects and how they can contribute to premature failure.

Who Should Attend?
Individuals associated with electronics packaging, package reliability, package failure analysis, and assembly process control/defects are encouraged to attend. The following are encouraged to attend. Managers. Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology. Engineers. Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who are challenged to solve process defects and packaging problems. Knowledge gained through this course will allow engineers and technologists to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.

Dr. Daniel F. Baldwin is the President and CEO of Engent, Inc.-Enabling Next Generation Technologies providing enabling manufacturing services and process technologies in the areas of microelectronics, flip chip, optoelectronics, and MEMS. He is one of the 2003 founding partners of Engent. He recently completed an Adjunct Associate Professor of Mechanical Engineering position at the Georgia Institute of Technology. He was a tenured Associate and Assistant Professor of Mechanical Engineering at Georgia Tech from 1995 through 2005. At Georgia Tech, he headed the Low Cost Flip Chip Processing program for the Packaging Research Center, the Advanced Interconnect Technologies research program for the Manufacturing Research Center, and the Low Cost Assembly Processing Program for the CBAR. Prior to joining the faculty, he was a Member of the Technical Staff at Bell Laboratories, Princeton NJ working on electronic product miniaturization. He was formerly the Vice President of Siemens' Advanced Assembly Technology Division. He also served as a research manager and research assistant at MIT's Laboratory for Manufacturing and Productivity from 1990 to 1994, a Draper Fellow at the Charles Stark Draper Laboratory in Cambridge MA from 1988 to 1990, and an Engineering Intern for Mitsubishi Electric, Kamakura, Japan in 1987. Dr. Baldwin received his S.M. and Ph.D. degrees in Mechanical Engineering from MIT in 1990 and 1994, respectively. Dr. Baldwin served as the Technical Program Chair of the IMAPS 2nd International Advanced Technology Workshop on Flip Chip Technology and the General Chair of the IMAPS 3rd International Advanced Technology Workshop on Flip Chip Technology. Dr. Baldwin was the recipient of the ASME Electrical and Electronics Packaging Division's Outstanding Young Engineer Award, 1998 and the Milton C. Shaw Outstanding Young Manufacturing Engineer Award, Society of Manufacturing Engineers, 1999. He has sixteen years of experience in the electronics manufacturing and packaging industries, eight U.S. Patents, over 230 scholarly publications, and expertise in electronics packaging, MEMS packaging, advanced materials processing and manufacturing systems design. Dr. Baldwin is a past President of the Surface Mount Technology Association (SMTA), and formerly on the Board of Advisors for the Society of Manufacturing Engineers/Electronics Manufacturing Division (SME/EM). He was on the editorial advisor board of Advanced Packaging magazine and HDI magazine. He is on the Board of Directors of Engent, Inc. and Akrometrix, LLC, and the Board of Advisors for IC Interconnect. Dr. Baldwin was also on the technical Board of Advisors of RFIDentics Corp. which was acquired by Avery Dennison Corp.

Break: 10:00 am - 10:20 am


Afternoon Professional Development Courses
1:00 pm - 5:00 pm

PDC6: Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging
Course Leaders: TJ Kiczenski, Aric Shorey, Corning, Inc.

Course Description:
The objective of this course is to build a foundation of understanding of engineered glass as a material that technologists can leverage in the development of advanced IC packaging applications. Starting from the fundamental principles of glass structure, composition and properties we will provide a broad overview of glass with a focus on unique attributes that make glass as an enabling material. Subjects to be covered will include strength and reliability, chemical durability, thermal behavior, associated thermal relaxation behavior, and electrical properties. Additionally we will review the platform alternatives as part of the "glass toolkit" available to semiconductor packaging development including various manufacturing (melt & form) approaches, the diversity of compositional options and a survey of glass processing options that can be adapted from adjacent glass technology space to advanced semiconductor packaging. Finally the course will illustrate with case studies how glass is contributing to emerging 3D-IC technologies and explore current and potential applications in advanced semiconductor packaging. We will focus on its role as a carrier for temporary bonding, integrated wafer for CMOS Image Sensor, and 2.5D and 3D glass interposers. Relative costs of glass will be discussed as an alternative to other materials for carriers and interposers.

Who Should Attend?
The target audiences include individuals or companies with little or no experience in using glass. Engineers, technical managers, scientists, buyers, and managers involved in materials, research and development, and 3D IC packaging.

Dr. TJ Kiczenski is a Research Associate with Corning Incorporated. His work includes investigations of the physics of glass relaxation, liquidus relationships in multicomponent glass forming systems, metallic glasses, and glass/glass and glass/ceramic composite materials. He is credited as the inventor or co-inventor of several Corning Display Technology products manufactured by the proprietary fusion process, including Corning Lotus Glass for low-temperature polysilicon display applications. He received his PhD in Geology and M.S. in Materials Science from Stanford University where he investigated the structure of fluorine in silicate and aluminosilicate glasses and his B.A. degree in Physics from Coe College where he studied alkali-germanate glasses. Aric Shorey, PhD, is a Sr. Technical Manager at Corning Incorporated working on the Semiconductor Glass Wafer program. He has BS/MS in Mechanical Engineering and a PhD in Materials Science - all from the University of Rochester. He has spent the majority of his career in material's finishing and characterization for the telecommunications, precision optics and semiconductor industries.

PDC7: Polymers for Electronic Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC

Course Description:
This course will provide a broad overview of polymers and the important structure-property-process-performance relationships for electronic packaging. Topics to be covered are thermosetting polymers versus thermoplastics, thermosetting polymer curing, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts). The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), capillary underfills, packaging substrate materials, encapsulants (mold compounds), and coatings. In most cases, adhesives, underfills, mold compounds and coatings are applied as a viscous liquid and then cured. The flow properties are critical to performance in high volume manufacturing. The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, rheology changes during curing), underfills, and mold compounds.

Who Should Attend?
Packaging engineers and R&D professionals involved in the development, production, and reliability testing of semiconductor packages would benefit from the course.

Dr. Jeffrey Gotro has over twenty-six years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He is an accomplished technology professional with demonstrated success solving complex polymer problems, directing new product development, and enabling clients to improve the financial impact of their polymer technologies. Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. Jeff is a nationally recognized authority in thermosetting polymers and he has received invitations to present lectures and short courses at national technical conferences. He has published 60 technical papers (including 4 book chapters) in the field of polymeric materials for advanced electronic packaging applications, holds 13 issued US patents, and has 8 patents pending. Jeff has a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science and a B.S. in Mechanical Engineering/Materials Science from Marquette University.

PDC8: Thermal and Mechanical Simulation Techniques - An Introductory Course for 3D Enablement Professionals
Course Leader: Kamal Karimanal, Cielution LLC

Course Description:
The industry is becoming increasingly aware of the fact that thermal and mechanical factors are crucial hurdles to the realization of TSV based 3 Dimensionally stacked IC products. These challenges are pervasively felt at all stages of the product development cycle starting from Layout, IC design, power management, assembly processing strategy, package design, and testing. Due to the need to narrow down from a myriad of costly choices even prior to test chip or prototype development, engineering simulation is an important tool at the disposal of the engineer. As a result, engineers from all IC design and packaging background who are tasked with the responsibility of enabling 3D ICs are interested in utilizing thermal and mechanical simulation. This is an introductory course on thermal and mechanical simulation techniques pertaining to 3D Through Silicon Stacking meant for engineering professionals involved in the enablement of TSV based 3D stacked SOCs. Thermal Modeling Techniques: Steady-State, Transient, Detailed and Compact. Modeling Tools and Techniques for 3D IC Thermal Management. Overview of mechanical challenges to 3D stacking: warpage, assembly Yield, CPI effects on Yield & reliability Mechanical Modeling Tools and Techniques for Technology development and Reliability. Mobility/stress distribution: Contributions from package, TSV and devices.

Who Should Attend?
Any Engineering professional involved in 3D enablement with interest in the Thermal and mechanical challenges. Also suited for technologists and managers interested in deploying engineering simulation as a strategic tool for understanding thermo-mechanical feasibility, risks and benefits of costly technological investments related to 3D TSV based products.

Kamal Karimanal is the Founder of Cielution LLC, which is an engineering simulation software and services company serving the electronics supply chain. Prior to starting Cielution, Dr. Karimanal has served in several engineering simulation focused roles at Fluent Inc, ANSYS Inc and Globalfoundries. Dr. Karimanal has contributed to several detailed and compact modeling methodologies which are being widely used by the electronics industry today. He has written several conference and journal papers and online application notes. Dr. Karimanal received his Ph. D in Mechanical Engineering from The University of Texas at Austin.

PDC9: MEMS Reliability and Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology

Course Description:
This course provides a comprehensive discussion of a broad array of MEMS packaging and reliability issues. An overview of the principles of operation, fabrication methods, and materials used in building MEMS structures will be presented as well. Because each MEMS device requires a distinctive packaging approach, practical examples and illustrations will be used to demonstrate uniqueness of solutions and interactions between micromachined structures and packaging. A full range of MEMS devices will be discussed while a particular emphasis will be placed on sensors and actuators used in industrial, medical, and automotive applications. Extensive case studies that will be used to most effectively demonstrate diverse packaging principles for devices such as accelerometers, pressure sensors, and digital micromirror devices. The course will be divided in 2 major sections: general MEMS competence; and packaging and reliability. The following major topics will be covered: fabrication technologies, materials, design and device physics, main MEMS types, integration aspects, selected industrial application, design considerations, types of packaging, quality control, reliability and failure analysis.

Who Should Attend?
While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will include a detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field. The participants will have the opportunity to gain knowledge about MEMS in general through the eyes of a packaging and reliability specialist.

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

PDC10: Basics of Conventional and Advanced Packaging
Course Leader: Syed Sajid Ahmad, Center for Nanoscale Science and Engineering, NDSU

Course Description:
The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and SMT and their solution will be outlined. Topics: Packaging characteristics and drivers. Types of packages and critical differences among them. Design selection to meet use and application environment. Step-by step manufacturing flow for plastic packages. Advanced packaging. Materials selection. Quality and reliability issues.

Who Should Attend?
It will help the attendees understand the effects of package configurations on their work and the effect of their work on chip packages. Personnel entering the packaging field will have a critical look at the quality, reliability and materials issues related to the development and manufacture of chip pacakages. Non-packaging personnel will learn ins and outs of chip packaging. Non-technical personnel will learn the material and manufacturing intricacies of simple looking chip packages.

Syed Sajid Ahmad contributed to quality and reliability enhancement of assembly processes at Intel (1979-89), especially wire bond. Ahmad also contributed to packaging development at National Semiconductor (1990) and managed quality at GigaBit/TriQuint (1990-91). His major work at Micron Technology (1991-2003) involved the development and implementation of advanced packaging. At the Center for Nanoscale Science and Engineering, Ahmad's focus is on enhancing research and manufacturing capabilities at the center in the areas of thin film, thick film, chip scale packaging (CSP) and surface mount technology (SMT). Ahmad has 34 international publications and presentations and holds 54 patents.

Break: 3:00 pm - 3:20 pm

Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 6:30 pm

Microelectronics Foundation Texas Hold'Em Tournament (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm

Register On-Line | Device Packaging Home

When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2.



DPC/GBC Premier Sponsors:

DPC/GBC Premier Sponsor: Solid State Equipment Corp.

DPC/GBC Premier Sponsor: Amkor Technology

DPC/GBC Premier Sponsor: ASE US, Inc.


 

Sponsor - Post-Conference Presentations USB Drives:

ALLVIA - Event Sponsor

Sponsor - Exhibit Reception, Lunch & Break:

Applied Materials - Event Sponsor

Sponsor - Conference Lanyards:
Hole Sponsor: NAMICS

Sponsor - 3D Panel:
3D Panel Sponsor: Invensas

Sponsor:
Sponsor: SANTIER

Sponsor:
Sponsor: Dow Corning

Sponsor:
Sponsor: Lam Research

Sponsor - Refreshment Breaks:
SETNA Corporation - Coffee Break & Golf Sponsor

Sponsor - Refreshment Breaks:
STATSChipPAC - Coffee Break Sponsor

Sponsor - Refreshment Breaks:
Sikama - Coffee Break Sponsor

Sponsor - GBC Speaker Dinner:
Kyocera - GBC Speaker Dinner Sponsor


 

"Eagle" Golf Sponsors:
"Eagle" Golf Sponsor: Solid State Equipment Corp.

DPC/GBC Premier Sponsor: ASE US, Inc.

"Birdie" Golf Sponsor:
"Birdie" Golf Sponsor: Amkor Technology


Golf Hole Sponsors:

Golf Hole Sponsor: NAMICS

Golf Hole Sponsor: Infinite Graphics

Golf Hole Sponsor: SETNA

3D Panel Sponsor: Invensas

Golf Hole Sponsor: Coining Inc/SPM

Golf Hole Sponsor: AGC Electronics America

Golf Hole Sponsor: PUTTIST, 3-Putt Killer

Golf Hole Sponsor: Dixon Golf


 

Student Paper Competition
Sponsor:


Student Paper Competition Sponsor - The Microelectronics Foundation


 

Media Sponsors:

Yole Developpement

I-Micronews

3D InCites - Media Sponsor

MEPTEC


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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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