Conference and Exhibition on
Radisson Fort McDowell Resort and Casino
Professional Development Courses (PDCs)
For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 10th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 6:30pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm. All are invited to register for this fun, new event which benefits the IMAPS Microelectronics Foundation.
PDCs are available for a separate fee/registration from the full conference (Tuesday-Thursday registration). When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact email@example.com with questions..
|7:00 am - 7:00 pm||
|7:00 am - 8:00 am||
|8:00 am - 12:00 pm||
Morning Professional Development Courses (PDCs)
|PDC1:Next Frontier in Electronics: Systems Scaling for Smart Mobile Systems
Course Leader: Rao R. Tummala, Georgia Tech 3D Systems Packaging Research Center
|PDC2: nanoMEMS Frontiers
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
|PDC3: Mechanical Design and Reliability Analysis in Microelectronics Packaging
Course Leader: Amaneh Tasooji, Arizona State University
|PDC4: Adhesion Fundamentals for Microelectronic Packaging
Course Leader: Raymond A. Pearson, Lehigh University
|10:00 am - 10:20 am||
|12:00 pm - 1:00 pm||
Lunch Only provided for those attendees registered for both Morning and Afternoon PDCs
|1:00 pm - 5:00 pm||
Afternoon Professional Development Courses (PDCs)
|PDC5: Industry Updates/Trends: 2.5D/3D, Flip Chip, MEMS, LED & Photonics (1Q2014-2Q2013)
Course Leader: Phil Creter, Creter & Associates
|PDC6: Package Level Integration - 2-D, 2.5-D and 3-D : Impact on Handheld Systems
Course Leaders: Dev Gupta, APSTL
|PDC7: Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, Center for Nanoscale Science and Engineering, NDSU
|PDC8: Polymer Challenges in 2.5D and 3D Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
|3:00 pm - 3:20 pm||
|5:00 pm - 6:30 pm||
Welcome Reception (All Attendees "GBC & DPC" Are Invited To Attend)
|7:00 pm - 10:00 pm||
Texas Hold'em Tournament (Limited Seating)
To Benefit the IMAPS Microelectronics Foundation
Morning Professional Development Courses
8:00 am - Noon
Monday, March 10
Transistor scaling, starting with the invention of transistor in 1949, made electronics the largest single, $1.5T global industry, serving a variety of individual industries that span computing, communications, consumer, automotive and others .The basis for this industry is a result of singular focus in transistor scaling, leading to a 5B transistor chip, involving dozens of semiconductor companies around the globe. But the electronics landscape is changing, driven by a new industry that integrates all these individual industries into so-called "Smart Mobile Systems" that promise to perform every imaginable function, in smallest size and lowest cost that every global person could afford. Such a new frontier, however, requires revolutionary technologies referred to as System Scaling, in contrast to transistor scaling during the last 60 years. Smart mobile systems are expected to drive unparalleled electronics technology paradigms in system miniaturization, functionality, and cost. The system scaling technologies are many that need to be explored, developed, integrated, interconnected, tested and commercialized. This course presents a vision, strategy and reviews status of system scaling technologies.
SYSTEMS SCALING TECHNOLOGIES: CHALLENGES, AND STATUS
The new system scaling technologies include new electrical, mechanical and thermal designs, new system substrate materials and processes, integration of ultra-thin actives, exploration and integration of ultra-thin passives, miniaturized and innovative thermal structures, thinfilm power storages such as batteries, and interconnections between all of these. These need to perform a variety of circuits and system functions that range from digital, analog, RF, wireless health, power, bio, MEMS and network sensors.
2D, 2.5D and 3D Substrates:
Current hardware approaches involve packaging of individual ICs that range from processors, memory, RF, MEMS and sensors as well as passive components and batteries. While some of these are packaged as MCMs and 3D wire-bond and stacked packages, there is very little system scaling. As such, mobile system companies see an eventual limit to functionality driven by the thickness limit of about 6000 microns. This limit can be largely eliminated by changing the current organic hardware platform which presents four main limitations for smart systems of the future: 1) lithographic ground rules below 5 microns and bump pitch below 30 microns, 2) thermal performance, 3) mismatch in TCE-driven, and moisture-driven reliabilities, and 4) warpage, as these organic packages are processed as ultra-thin packages. The lithographic ground rule limitation is due to the visco-elastic nature of polymers and thus is limited to about a 50 micron pitch area array. The thermal conductivity of polymers is about two to three orders of magnitude less than silicon. The mismatch in TCE between Si and organic is huge, creating stresses on both the interconnections and the ultra-low-k on-chip dielectrics. The warpage is due to many factors including high TCE and low modulus.
Si substrates address most of the above challenges but they have two shortcomings: low electrical performance and high cost. Glass is being developed to address these and others. But panel-based substrate is not being manufactured.
Off-chip Electrical and Optical Interconnections: Interconnections have been largely driven by the use of solders onto copper pads, bumps or pillars. But these solder-based interconnections limit both bump pitch as well as thermo-mechanical and electro-migration performances. Short copper interconnections formed at low temperature address these limits. The Georgia Tech team has demonstrated such a technology for the first time overcoming the shortcomings, thus starting a new era without solders.
As electrical interconnections reach limits, short optical interconnections are envisioned. Optical interconnections, in the past, have had two shortcomings: cost and long side-by-side chip interconnections. The recent breakthroughs address both these limits by large panel-based processing of glass with through-glass vias and by short 3D optical interconnections.
Board level Interconnections: As the substrate technology moves to large, low-TCE organic, glass or silicon interposers or packages, board-level interconnections become problematic. This problem is being addressed by a variety of stress-decoupling mechanisms such as polymer collars, compliancy and stress-buffer interfaces.
Advanced Passives and their Integration with Actives: Passives remain the largest number of components in a typical electronic system. Not only are they too many, they are bulky, taking up of lot of space but are also too far from actives for them to be effective. Two new concepts referred to as 3D IPD for ultra-miniaturized passive integration and 3D IPAC for ultra-short passive to active integration address these limits. Unlike the previous IPDs, both are 3D structures. A variety of RF and power components have been demonstrated recently.
Electrical Designs: Optimized Signal and Power integrity, and EMI Designs remain major challenges as the new packaging structures are miniaturized with close proximity of the components, and as the power-reduction and frequency needs escalate. Designs that overcome or suppress cavity resonances become very important. A number of new or advanced solutions such as optimized power and ground planes as well as the use of coaxial and decoupling capacitors are being demonstrated.
Thermal Designs: As system scaling continues from current macro-packaging to nano-scaled systems, even portable systems face thermal challenges. A number of recent advances in through-copper vias, other hot-spot thermal transfer and to board- coupling are being pursued.
Mechanical Designs: Warpage and interconnection reliability become two major challenges as substrates migrate to below 100 microns in the short term and systems are miniaturized to nanoscale in the long term. A systematic approach to address both is needed.
Who Should Attend?
This is a new course on a new strategic topic of great interest to industry R&D executives, senior managers and technical leaders who are developing both short- and long-term strategies for their companies in every electronics technology.
Professor Rao Tummala is a Distinguished and Endowed Chair Professor, and Founding Director of NSF ERC, called PRC at Georgia Tech, known as the world's premier systems packaging Center pioneering System Scaling technologies, producing the most cross-disciplinary engineers and transferring both to global industry. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering the first plasma display and low temperature co-fired(LTCC) multichip electronics for mainframes and servers. Prof. Tummala published about 500 technical papers, holds 90 patents and inventions; authored the first modern Microelectronics Packaging Handbook, the first undergrad textbook, 'Fundamentals of Microsystems Packaging', and first book introducing the System-On-Package technology. His Georgia Tech PRC Center is considered the number 1 Academic Center having produced more than 1000 Ph.D, MS and BS students, 2000 publications and collaborating with more than 100 companies in US, Europe, Japan and Korea. He is a Fellow of IEEE, and a member of National Academy of Engineering in US and India . He was a past President of IEEE-CPMT and the IMAPS Societies.
This course will explore futuristic concepts that combine MEMS and nanoscience. The merging of nanoscience and microelectromechanical systems presents an opportunity for development of next generation technologies for use in computers, wireless communication, biomedicine, and a variety of sensors.
The course will start by providing an overview of the MEMS principles of operation, fabrication methods, and in particular the materials used in building MEMS structures. Variety of MEMS devices will be discussed while a particular emphasis will be placed on MEMS in wireless communication; and sensors and actuators used in industrial, medical, and automotive applications.
The introduction to nanoscience will start by evaluating how size can influence the properties of nanoscale systems. The nanomaterial synthesis and characterization methods will be explored next. The highly speculative discussion will offer a possibility for using nanoscale phenomena for technological purposes related to MEMS. The emphasis will be placed on merging the nanoscience with MEMS fabrication principles, design considerations, integration aspects, and packaging.
In the third section, the integration of power supplies and energy storage devices with MEMS and nanoMEMS devices will be discussed. These devices will be the key in the packaging and for autonomous function of future devices. The general concept of nanoscience for energy will be discussed, in particular nanoscale batteries, fuel cells, hydrogen production, solar cells, and biological materials for energy production.
Who Should Attend?
The course is open to anyone with general understanding of the physics, chemistry, and material science. The participants will have the opportunity to explore highly speculative, futuristic concepts and develop visionary views of the technological possibilities. The course is open to participants with no prior MEMS, nantotechnology, or power sources knowledge and would provide a reasonably broad general introduction into all three areas of technology.
Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.
The objective of this course is to provide an overview of mechanical design and discuss the reliability analysis and tools used in microelectronics packaging. Mechanical design requirements and analysis approaches are reviewed, and Traditional/Classical and Damage-Tolerant (Fracture-Mechanics and LEFM) approaches are discussed. Stress-strain response (including thermal loading due to CTE-mismatch), materials behavior and constitutive models, and failure mechanisms (brittle/ductile fracture, DBTT, creep, and fatigue) are reviewed. Closed form solutions and analytical approaches (FEM, Finite Element Methods) are presented. Reliability analysis and tools used in ensuring mechanical integrity are discussed. Methodology used in determining acceleration factor (AF) for predicting package performance/reliability under 'use condition' is presented. Statistical methods and Life prediction methodologies used in mechanical analysis and component reliability assessment are discussed.
Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with microelectronics packaging and general device assembly technologies.
Dr. Amaneh Tasooji has more than 25 years of industrial and academic experience in engineering and manufacturing. She received her Ph. D. in Materials Science and Engineering from Stanford University in 1982, and has B. S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, design, manufacturing, quality/reliability in many industries such as microelectronics, aerospace, and nuclear energy. She has had many technical and leadership responsibilities while at Honeywell/AlliedSignal and has developed many materials behavior, life prediction, and reliability models and methodologies. Dr. Tasooji has developed and delivered many graduate and undergraduate engineering courses (e.g., 'Fundamentals of Micro-electronic Packaging', 'Advanced Packaging Analysis and Design', 'Nuclear Materials', 'Structure and Properties of Materials', 'Physical Metallurgy', etc.) at Arizona State University. She has conducted many globally-based workshops on microelectronics packaging in Asia, South America, and at iMAPS PDC conference in US, and has leveraged new technology and e-learning concepts in delivering her courses. Amaneh has leveraged new technology and e-learning concepts in developing and offering conventional (face-to-face) and hybrid courses (on-campus and distance training) at ASU.
Polymers are widely used in electronic packaging. The lack of adhesion can adversely affect reliability as well as package performance. The intention of this course is to review the fundamentals of adhesion and apply them to interfaces found in Plastic-Quad Flat Packs (PQFP), chip-scale packages (CSP), and Flip-Chip (FC) assemblies. Adhesion issues in molding compounds, die attach adhesives, and underfill resins will be discussed By the end of the course, you should know how to choose the proper tools to predict and measure adhesion.
Who Should Attend?
Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development.
Dr. Raymond A. Pearson joined the Materials Science and Engineering Department at Lehigh University in August of 1990 after obtaining his doctorate in Materials Science and Engineering from University of Michigan. Prior to graduate school, Ray had worked for seven years with General Electric Company: from 1980-1984 as an associate staff member at GE's Corporate Research and Development Center in Schenectady, New York and from 1984-1987 as a materials specialist at GEPE's Product Technology Center in Bergen op Zoom, the Netherlands. His research interests include all aspects of processing, deformation, yield, and fracture of polymers. He has extensively in the area of fracture mechanisms and adhesion. In 2001, Ray became Director of the Center for Polymer Science & Engineering. He has worked closely with organizations such as the Semiconductor Research Corporation and SEMATECH.
Break: 10:00 am - 10:20 am
Afternoon Professional Development Courses
1:00 pm - 5:00 pm
This NEW OVERVIEW focuses on five major topics of the 2014 Device Packaging Conference, independently reviewing leading edge technical developments featuring the latest in packaging updates abstracted from 30+ peer-reviewed white papers (1Q2014 to 2Q2013) to highlight technical innovations. They are organized into the following groups:
2.5D/3D (Status/market, wide I/O-logic prototype, stacked silicon FPGA, 1000+ IO Package-on-Package, performance comparison of glass & silicon interposers, advanced CUF-NCP-MUF, 3D-metrology solutions, polymer and damascene RDL, low cost thin wafer handling, low temperature WL Si-Si bonding, toughened benzocyclobutene);
Flip Chip (Status/market, large chip low CTE chip-scale-package, overview of molded-underfill, novel microbump assembly using damascene copper pillars, advanced lidded FC applications, high thermal inter-chip-fill);
MEMS (Status/market, chip-on-chip for MEMS, accelerometer heart transplant, hermetic wafer level packaging of MEMS, vacuum packaging of MEMS);
LED Packaging (Status/market, very high power LED, advanced microfluidic cooled LED, wafer level embedded ultra-thin LED); and
Photonics (Status/market, 1.3 Tb/s optical interconnect module, wafer-level polymer micro-lens array, optical packaging of photonic devices).
Technical inputs are from leading industrial/academic/press organizations: Corning, DISCO, Dow-Electronic Materials, Dow Corning, EE Times, Fraunhofer, IBM, IC Insights, IFTLE, Intel, Invensas, ITRI, ITRS, Kyocera, Mitsubishi, NAMICS, Qualcomm, Rudolph, Samsung, Shinko, SPIL, STMicroelectronics, TSMC, Xilinx, Yole and others.
Attendees receive a 300+ slide handout including comprehensive references for more detail.
Who Should Attend?
This course's target is the time-constrained participant with little or no extra time to constantly review daily news releases and/or attend major symposia/workshops to stay current with the latest technological developments in new advanced packaging technology.
It emphasizes Device Packaging Conference 2014 topics in 2.5D/3D, Flip Chip, MEMS, LED & Photonics and is designed for all levels of engineering. It primarily includes advanced packaging concepts for senior engineers/scientists but since the course contains a short review of current single chip and advanced wafer levels of packaging, it is also ideal entry-level technicians/engineers, QA, sales/marketing, purchasing, safety administration, program management.
Phillip Creter is a consultant (Creter & Associates) with 30 years of microelectronics experience at Polymer Flip Chip Corporation, Mini-Systems, GTE, Itek Corporation. Past positions at GTE included Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), and Principal Investigator of GTE IR&D Projects. Other positions elsewhere included management in Projects/Process Engineering, Process Development, Materials Engineering/Manufacturing Engineer, receiving many awards of distinction.
Creter has been developing and teaching industry-level microelectronics courses for training since 1997. He has continuously taught Professional Development Courses since 2004 for online webinars and national microelectronics symposia/workshops. He is a well-known presenter having published technical papers in IEEE Transactions, Solid State Technology, High Density Interconnect, Circuits Manufacturing, Insulation Circuits, others. He has chaired many technical symposia sessions, given numerous technical presentations, is a US patent holder. He is an active certified Department of Homeland Security instructor, a Life member of IMAPS, elected Fellow of the Society, and has held several executive committee offices both locally/nationally.
This 4-hour course will cover both physical and electrical aspects of Advanced Packaging already in use (e,g. PoP) or expected to be used (3-d stack using TSVs) in performance driven handheld systems like Smart Phones in order to predict future trends and Portable systems like Smart Phones, Tablets and now Wearable devices have become high growth drivers for the whole electronics industry specially for devices e,g. Processors, Memory, RF, MEMS sensors to name a few. Due to their compact form factor and emphasis on performance, these handheld systems have also become large users of Advanced Packaging technologies like flip-chip, WLP, SIP etc. They also use package on package modules (PoP), a testable and non - disruptive approach to 3-d stacking using current interconnect technologies. Electrical performance of this PoP package is becoming ever more critical as higher data - transfer rates (bandwidth) is required in the very competitive handheld systems to drive displays of ever higher resolution and larger size. Several years ago it was being predicted that PoP packages in Smart Phones will soon get replaced by the latest version of Advanced Packaging under development, namely 3-d stacking of dies using Through Silicon Vias (TSVs). But this has not yet happened.
In this course we will examine the electrical performance of PoP and various proposed configurations of 2.5-d and 3-d packages for Processor - Memory modules, discuss in some detail the current status of development of these technologies (design, materials, process, integration & reliability) around the world and issues. Last we will review efforts to improve the classical PoP package, such as the BVA and Super-PoP technologies from both a physical and electrical standpoint.
- description of handheld systems like typical Smart Phones, Tablets and Games, packaging used and evolution
- key selection criteria for packages in Smart Phones, form factor, testability, cost, electrical performance, heat removal
- key modules e,g. Applications Processor, description of components e,g. SoC and DRAM and their operation, evolution of SoC and Memory over several generations, performance trends
- analyses of performance metrics like bandwidth and power consumed to transfer data and equations from first principles
- electrical modeling of data transfer between SoC and DRAM, DRAM and display drivers, waveforms, signal distortion / integrity and effect on bandwidth, effect of package & board design, scenarios for improving performance,
- understanding 2-d, 2.5-d and 3-d integration by packaging from electrical performance & design standpoint,
- various strategies / package configuration for 2-d, 2.5d and 3d, overview of technologies under development, modeling & measurement of performance (Bandwidth, power consumption)
- physical details of 2.5-d and 3-d packaging technologies, materials / process flow for etching and filling TSVs. Yield issues, Effect of via fill material on stress induced on surrounding devices, keep - out zones
- impact of design and process choice on the cost of 3-d die - stacking processes using TSVs
- evolutionary 3-d packaging technologies (PoP) to meet future needs (Bandwidth, Power consumption) Smart Phones,
- BVA, Super PoP technologies and evaluation
- likely roadmap (based on theoretical analyses) for implementation of 2.5-d and 3-d in portable systems
Who Should Attend?
For the very first time both electrical and process details of 3-d stacking of dies will be addressed in a single course and should be useful for Engineers, Managers and Market Analysts.
Dr. Dev Gupta has frequently offered PDC courses on Advanced Packaging topics at IEEE Conferences and Semicon. He has 25 years of experience in innovating Advanced Packaging technologies that are now industry standards. In the early '90s at Motorola SPS he developed electroplated solder bump flip chip technology for ASICS including plating, assembly, robotic bonders using machine vision. By the mid '90s he pioneered the world's first uPillar bump FC technology ( 45 um pitch, Sn capped) for GaAs PAs in Flip phones. This included tools & processes for bumping in thick photo-resists, fast cycle thermo-compression FC bonding and robotics, integrated microwave passives. He had also led the process development for Motorola's modifications to IBM C-4 bumping process. At Intel Dr. Gupta was the Program Manager for Organic Substrate technology development and ramp to high volume manufacturing at overseas suppliers. The process developed by his team succeeded in dramatically improving substrate yield and enabled the widespread adoption of flip chip technology. At APSTL he is responsible for development and licensing of breakthrough Packaging technologies for portable systems, such as the Super-PoP.
The course presents manufacturing, materials, quality and reliability information in simple terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their quality and reliability implications and their applications will be discussed. The course will look at the design considerations and material selection to meet use and application environments. Step-by-step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in the manufacture of semiconductor packages. Advanced packaging will be introduced including wafer level packaging. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and SMT (surface mount technology) and their solutions will be outlined.
Who Should Attend?
Packaging and non-packaging personnel will learn ins and outs of chip packaging. It will help them understand the differences in and impact of package configurations on their work and the effect of their work on chip packages. Personnel entering the packaging field will have a critical look at the quality, reliability and materials issues related to the development and manufacture of chip packages. Non-technical personnel will learn the material and manufacturing intricacies of simple-looking chip packages.
Syed Sajid Ahmad contributed to quality and reliability enhancement of assembly processes at Intel (1979-89), especially wire bond. Ahmad also contributed to dense packaging development at National Semiconductor (1990). He managed quality at GigaBit/TriQuint (1990-91). His major work at Micron Technology (1991-2003) involved the development and implementation of advanced packaging. At the Center for Nanoscale Science and Engineering, Ahmad's focus is on enhancing research and manufacturing capabilities at the center in the areas of thin film, thick film, chip scale packaging (CSP) and surface mount technology (SMT). Ahmad has 35 international publications and presentations and holds 54 patents.
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging with a focus on 2.5D and 3D packaging, 2) learn why specific chemistries are used depending on the application 3) learn the key polymer challenges, solutions, and processes for 2.5D and 3D packaging 4) develop a foundation in rheology and rheological issues in electronic packaging (such as dispensing, underfill flow, non-conductive paste rheology for wafer applied underfills, etc.). Participants are invited to bring problems for discussion.
Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.
Dr. Jeff Gotro has over thirty years’ experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is a nationally recognized authority in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the Product Development and Management Association (PDMA), American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), and the International Microelectronics and Packaging Society (IMAPS).
Break: 3:00 pm - 3:20 pm
Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 6:30 pm
Microelectronics Foundation Texas Hold'Em Tournament (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm
When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2.