KESTER

11th International Conference and Exhibition on
Device Packaging
www.imaps.org/devicepackaging

WekoPa Resort and Casino
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 17-19, 2015
Exhibition and Technology Showcase
March 17-18, 2015
Professional Development Courses
March 16, 2015
NEW** GBC Plenary
Session on IoT

March 18, 2015

Early Registration & Hotel Deadlines: February 17, 2015

Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC
 

REGISTER ONLINE
Registration Information | Hotel Reservations
Technical Program | Professional Development Courses (PDCs)
Exhibition Details | Floorplan | 2015 Exhibitors | 2014 Exhibitors


Professional Development Courses (PDCs)

For those wishing to broaden their knowledge of device packaging, a selection of half-day courses and one full-day course (Intro to Microelectronics) will be offered on Monday, March 16th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The full-day "Intro" course will run from 8:00am until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 7:00pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm. All are invited to register for this fun, new event which benefits the IMAPS Microelectronics Foundation.

PDCs are available for a separate fee/registration from the full conference (Tuesday-Thursday registration). When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact bschieman@imaps.org with questions..

7:00 am - 7:00 pm
Registration
7:00 am - 8:00 am
Continental Breakfast
8:00 am - 12:00 pm FULL-DAY PDC – 8:00am-5:00pm

PDC1:Introduction to Microelectronics Packaging (8-hour)
Course Leader: Tom Green, TJ Green & Associates
Morning Professional Development Courses (PDCs)
PDC2:MEMS and nanoMEMS: Devices and Applications
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
PDC3: Interposers for High Performance Computing, Mobile and Emerging IoT Applications
Course Leader: Venky Sundaram, Georgia Tech. PRC
PDC4: IC Package Technology Selection and Cost Reduction Using Supply Chain Modeling
Course Leader: Chet Palesko, SavanSys Solutions LLC
PDC5: Adhesion Science & Technology
Course Leader: Kashmiri Mittal, Daetec

(Two-Part PDCs – Part 2 “Temp Bonding” in afternoon – Add. Fee)
10:00 am - 10:20 am
Break
12:00 pm - 1:00 pm
Lunch Only provided for those attendees registered for both Morning and Afternoon PDCs
1:00 pm - 5:00 pm
Afternoon Professional Development Courses (PDCs)
PDC6: Introduction to Fan-Out Wafer Level Packaging (FO-WLP)
Course Leader: Beth Keser, Qualcomm Technologies, Inc.
PDC7: Polymers for Electronic Packaging
Course Leaders: Jeffrey Gotro, InnoCentrix, LLC
PDC8: Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, Center for Nanoscale Science and Engineering, NDSU
PDC9: Temporary Bonding of Electronic Devices (with "Hands On" Equipment demonstrations)
Course Leaders: Jared Pettit, John Moore, Daetec

(Two-Part PDCs – Part 1 “Adhesion Science” in morning – Add. Fee)
3:00 pm - 3:20 pm
Break
5:00 pm - 7:00 pm
Welcome Reception (All Attendees Are Invited To Attend)
7:00 pm - 10:00 pm
Texas Hold'em Tournament (Limited Seating)
To Benefit the IMAPS Microelectronics Foundation


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Full-Day Professional Development Courses
8:00 am - 5:00 pm
Monday, March 16

PDC1: Introduction to Microelectronics Packaging (8-hour PDC: 8:00am-5:00pm)
Course Leader: Tom Green, TJ Green & Associates
FULL-DAY (8-hr.) PDC: 8:00am – 5:00pm | $600 (Through 2/17/2015) - $650 (after 2/17/2015)

Course Description:
The instructor begins by broadly describing packaging terminology and reviews the alphabet soup of acronyms used throughout the electronics industry; terms such as: DIP, LCC, QFN, Hybrids, BGA, CSP, Flip Chip, 3D, TSV, WLP etc. The technology is then broken down by industry segments, beginning with high volume commercial packaging technology used in cell phones, tablets and handheld wireless devices, automotive, telecom and then progressing onto specialized packaging for low volume complex devices used in military/space/medical products as well as, RF microwave circuits, optoelectronics, LEDs and next generation packaging of MEMS and sensors. Lots of pictures, short video clips and pass around samples, along with simple explanations will help the attendee understand the technology drivers and key aspects of microelectronic packaging technology in a fun and interactive way. Besides a good overview the student will understand the basics of how to assemble and package single and multi-chip microcircuits, with a focus on the materials and processes and the associated equipment sets needed to support the industry. Wafer processes, probing and dicing, substrate selection, interposers, die attach using solders and epoxy, AU/Al/Cu wirebond processes, undefills, encapsulations, dam and fill, glob tops, transfer molding and hermetic packaging are all be reviewed with an eye on the important technical issues and industry drivers. Current hot topics and future industry trends will finish out the day and there will be plenty of time for questions.

Who Should Attend?
This overview course is intended for those unfamiliar with microelectronics packaging technology. People in sales, purchasing, program management, new engineers, managers, equipment/material suppliers, people new to this industry or anyone looking to get a broad industry overview and review of the industry drivers, history and future trends are welcome to attend.

Mr. Tom Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of public courses around the globe and in plant at major corporations and consults for a variety of medical device companies. He has thirty two years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, hermetic seal and leak testing processes. He has gained valuable experience over the past ten years in packaging and testing of devices for use as Class III medical implants and is often called on as an expert witness for hermeticity related failures. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

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Morning Professional Development Courses
8:00 am - Noon
Monday, March 16

PDC2: MEMS and nanoMEMS: Devices and Applications
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)

Course Description:
This course will explore futuristic concepts that combine MEMS and nanoscience. The merging of nanoscience and microelectromechanical systems presents an opportunity for development of next generation technologies for use in computers, wireless communication, biomedicine, and a variety of sensors. The course will start by providing an overview of the MEMS principles of operation, fabrication methods, and in particular the materials used in building MEMS structures. Variety of MEMS devices will be discussed while a particular emphasis will be placed on MEMS in wireless communication; and sensors and actuators used in industrial, medical, and automotive applications. The introduction to nanoscience will start by evaluating how size can influence the properties of nanoscale systems. The nanomaterial synthesis and characterization methods will be explored next. The highly speculative discussion will offer a possibility for using nanoscale phenomena for technological purposes related to MEMS. The emphasis will be placed on merging the nanoscience with MEMS fabrication principles, design considerations, integration aspects, and packaging. In the third section, the integration of power supplies and energy storage devices with MEMS and nanoMEMS devices will be discussed. These devices will be the key in the packaging and for autonomous function of future devices. The general concept of nanoscience for energy will be discussed, in particular nanoscale batteries, fuel cells, hydrogen production, solar cells, and biological materials for energy production.

Who Should Attend?
The course is open to anyone with general understanding of the physics, chemistry, and material science. The participants will have the opportunity to explore highly speculative, futuristic concepts and develop visionary views of the technological possibilities. The course is open to participants with no prior MEMS, nantotechnology, or power sources knowledge and would provide a reasonably broad general introduction into all three areas of technology.

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

PDC3: Interposers for High Performance Computing, Mobile and Emerging IoT Applications
Course Leader: Venky Sundaram, Georgia Tech PRC
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)

Course Description:
In the fast moving technology domain of interposers, this course will provide the latest updates as well as an introduction to interposer technologies, market drivers, application examples and infrastructure evolution, covering silicon, organic and glass interposers. Interposers bridge the interconnect gap between back end of the line (BEOL) pitch and current organic BGA packages. Interposers started out as a 2.5D multi-die integration step towards full 3D IC stacking. However, they are now viewed as a system integration platform with pervasive applications now and into the future. In the past couple of years, the technology development and manufacturing infrastructure maturity has been progressing rapidly. The first volume products using silicon interposers are expected to hit the graphics market in 2015 integrating high bandwidth memory (HBM) and GPUs. Several other applications are also exploring product designs based on interposer concepts. It is certainly an exciting time for interposer technologies. Emerging alternatives such as glass and new organic interposers are promising cost reduction from wafer based silicon interposers, that should enable a much broader adoption of interposers. This year's PDC by one of the top interposer experts in the world, includes significant new material covering the latest advances in 2.5D and 3D interposers. The course will address both fundamentals of interposer technology, as well as applications and supply chain infrastructure. An extensive review of three major interposer options being pursued, namely, silicon, organic and glass, will be provided. The course will be interactive and include audience Q&A and samples of latest interposer demonstrators will be passed around for a hands-on experience.

Who Should Attend?
This is a must attend course for anyone interested in state-of-the-art interposer technologies. The course is especially valuable to semiconductor, electronics systems, and packaging industry personnel in engineering, management, corporate technology strategy, pathfinding and marketing teams.

Dr. Venky Sundaram is a Research Professor and manages the Industry Research Programs at the 3D Systems Packaging Research Center (PRC), Georgia Tech. He is the Program Director for the largest Low Cost Glass Interposer & Package (LGIP) industry consortium with more than 30 active global industry members. He is a globally recognized expert in 3D systems packaging, and has pioneered major technologies including embedded RF passives in organic substrates, chip-last die embedding and glass interposers. His research expertise is in the areas of System on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components, bio-medical device packaging, LED packaging and systems integration research. He has mentored more than 15 PhD and MS students, and teaches a laboratory course every Fall on SOP Substrates, ECE/MSE 4755. He is a co-founder of Jacket Micro Devices, an RF/wireless start-up acquired by AVX. Dr. Sundaram has served as session chair at major global packaging conferences, serves on the Advanced Packaging Committee of SEMI, is the co-chairman of the IEEE CPMT Technical Committee on High Density Substrates, serves on the Editorial Advisory Board of Chip Scale Review magazine, and is in the Executive Council of IMAPS as Director of Education Programs. Dr. Sundaram has won several best paper awards and has 15+ patents and 150+ publications. He received his BS from IIT Mumbai, and MS and PhD in Materials Science and Engineering from Georgia Tech.

PDC4: IC Package Technology Selection and Cost Reduction Using Supply Chain Modeling
Course Leader: Chet Palesko, SavanSys Solutions LLC
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)

Course Description:
Choosing the right packaging technology and the right supplier is crucial to product success. The growing complexity of the supply chain itself coupled with the ever increasing choice of technologies - wafer level packaging, fan-out wafer level packaging , 2.5D silicon, 3D silicon, embedded die, etc.- makes it impossible to fully optimize packaging choices and understand cost trade-offs without modeling the cost structure and capabilities of your supply chain. In this course, we will examine how OEMs and suppliers can collaborate to develop a model which optimizes product manufacturing cost for IC packages. This modeling approach has been successfully used by a number of major OEMs and suppliers in North America, Europe, and Asia to match design technology choices with supplier competencies. Yields are improved and true cost reduction is achieved across the entire supply chain - not just in one place. The packaging technologies included in this course are flip chip PBGA, wire bond PBGAs, 2.5D silicon, fan-out wafer level packaging, and embedded die. Course participants will learn key cost and yield drivers for the five package types listed above. They will also learn how to gather key modeling data and build supply chain collaboration cost models - even in an environment where confidential data is not available.

Who Should Attend?
This course is designed for anyone who involved in packaging technology and selection. This includes system designers, package designers, procurement personnel, design managers, and product managers.

Mr. Chet Palesko is currently President of SavanSys Solutions LLC. SavanSys Solutions LLC (www.savansys.com) provides cost modeling services and software to both suppliers and OEMs. Mr. Palesko has developed dozens of electronic manufacturing cost models for major telecommunication, computer, and aerospace companies. He spent 12 years at Mentor Graphics in a variety of roles including general management, engineering, marketing, and sales. In 1995, Mr. Palesko co-founded Savantage Inc., where he led the global development and sales of SavanSys.

PDC5: Adhesion Science & Technology (Part 1, Morning)
Course Leader: Kashmiri Mittal, Daetec
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)
(Intended to be a Two-Part PDC -- Part 2 “Temp Bonding” in the afternoon for an additional fee)

Course Description:
Part 1: Adhesion plays an important role in many technologies and industries, viz., automotive, thin films, optics, printing, medical, coatings, paint and so on. Adhering two materials require several properties to be coordinated in the form of chemistry and mechanical processing to achieve a good bond. Understanding these factors and controlling them during manufacturing is important for success. Bond durability (exposure to process chemicals, moisture, corrosives, etc.) is valuable to sustain the life of the product. The following will be discussed: Surface Contamination and Cleaning, Theories or Mechanisms of Adhesion, Contact Angle and Wettability, Interfacial Interactions, Surface Modification, Adhesion Promoters, Adhesion Aspects of Thin Films, Adhesive force measurement.

Intended to be a Two-Part PDC - Part 2 “Temporary Bonding of Electronic Devices” being held in the afternoon for additional fee. See PDC9 details below.

Who Should Attend?
Packaging scientists, engineers, managers, and others charged with responsibilities related to substrate or component bonding that is permanent or temporary.

Dr. Kashmiri Mittal is an internationally recognized authority in the area of surface and adhesion science, has edited over 100 books, and has held several board positions, including Editor-in-Chief of the Journal of Adhesion Science and Technology. Kash is the founding editor of the new journal Reviews of Adhesion and Adhesives as well as the new Book Series entitled Adhesion and Adhesives: Fundamental and Applied Aspects.

Break: 10:00 am - 10:20 am

 

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Afternoon Professional Development Courses
1:00 pm - 5:00 pm

PDC6: Introduction to Fan-Out Wafer Level Packaging (FO-WLP)
Course Leaders: Beth Keser, Qualcomm Technologies, Inc.
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)

Course Description:
Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 5 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, and benchmarking.

Who Should Attend?
Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Both newcomers and experienced practitioners are welcome.

Dr. Beth Keser has over 17 years’ experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s development of materials and packaging technologies for the semiconductor industry has resulted in 8 patents, 10 patents pending, and over 40 publications in this area. Currently, Beth is the Fan-Out Wafer Level Packaging Technology Manager at Qualcomm, San Diego. Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling. In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology. Beth also volunteered as WLP Track co-chair at IMAPS Device Packaging Conference from 2006-2009.

PDC7: Polymers for Electronic Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)

Course Description:
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application 3) learn the fundamentals of polymer characterization related to electronic packaging 4) develop a foundation in rheology and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Dr. Jeff Gotro has over thirty-two years of experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is a recognized authority in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff is a Fellow of IMAPS and was awarded the John A. Wagnon Technical Achievement Award in 2014 for his technical contributions in the area of polymers in electronic packaging. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), and IMAPS.

PDC8: Basics of Conventional and Advanced Chip Packaging
Course Leader: Syed Sajid Ahmad, Center for Nanoscale Science and Engineering, NDSU
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)

Course Description:
The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and assembly and their solution will be outlined.

Who Should Attend?
Non-packaging personnel will learn ins and outs of chip packaging. It will help them understand the effects of package configurations on their work and the effect of their work on chip packages. Personnel entering the packaging field will have a critical look at the quality, reliability and materials issues related to the development and manufacture of chip packages. Non-technical personnel will learn the material and manufacturing intricacies of simple looking chip packages.

Syed Sajid Ahmad contributed to quality and reliability enhancement of assembly processes at Intel (1979-89), especially wire bond. Ahmad also contributed to packaging development at National Semiconductor (1990) and managed quality at GigaBit/TriQuint (1990-91). His major work at Micron Technology (1991-2003) involved the development and implementation of advanced packaging. At the Center for Nanoscale Science and Engineering, Ahmad's focus is on enhancing research and manufacturing capabilities at the center in the areas of thin film, thick film, chip scale packaging (CSP) and surface mount technology (SMT). Ahmad has 41 international publications and presentations and holds 54 patents.

PDC9: Temporary Bonding of Electronic Devices (Part 2, Afternoon)
Course Leaders: Jared Pettit, John Moore, Daetec
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/17/2015) - $450 (after 2/17/2015)
(Intended to be a Two-Part PDC -- Part 1 “Adhesion Science & Technology” in the morning for an additional fee)

Course Description:
Part 2: An application-oriented part of the tutorial that focuses on everything from temporarily bonding wafers & displays to small die and other components. This period involves the demonstration of bonding and measurement of adhesion force using materials with various tensile and elastic properties. Separation of substrates will be defined by form and composition (rigid and flexible, organic and inorganic). Onsite equipment will be used in conjunction with class members creating temporary bonds on parts with challenging configurations.

"HANDS ON" Demonstrations! Temporary bonding challenge: bring your workpiece as flexible or rigid, small or large, and Daetec will create several options to affix that item and allow you to witness on-site the affixing and removal of such items. Due to equipment limitations, please limit your substrate to 6" round or 4" square maximum, and the ability to OM view by low magnification..

Intended to be a Two-Part PDC - Part 1 “Adhesion Science & Technology” being held in the morning for additional fee. See PDC5 details above.

Who Should Attend?
Packaging scientists, engineers, managers, and others charged with responsibilities related to substrate or component bonding that is permanent or temporary.

Mr. Jared Petit is technical director at Daetec, has co-authored many publications and patents in the area of coatings and cleaners, and has been creating new temporary bonding products and processes for a host of electronic devices.

Mr. John Moore is founder of Daetec, his third company, which provides product development services for the electronics market, where over the last 10yrs has completed 30 projects for leading suppliers and end users, creating some of the leading temporary bonding products for wafer and displays.

Break: 3:00 pm - 3:20 pm

Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 7:00 pm

Microelectronics Foundation Texas Hold'Em Tournament (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm

Device Packaging Home

REGISTER ONLINE

When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2.

 

Device Packaging/GBC Sponsors

Premier Sponsor:
DPC/GBC Premier Sponsor: VEECO

Premier Sponsor:

Golf Hole Sponsor: Amkor Technology

Premier Sponsor:
DPC/GBC Premier Sponsor: ASE US, Inc.

Corporate Sponsors

SPTS - Corporate Sponsor

Mentor Graphics - Corporate Sponsor
Event Sponsors
Sponsor - Badge Lanyards:
Hole Sponsor: NAMICS
Sponsor - GBC Speaker Dinner:
Kyocera - GBC Speaker Dinner Sponsor
Poster Session "Happy Hour":
Sponsor: Lam Research

Sponsor - Lunches:
Applied Materials - Event Sponsor

Sponsor - Evening Sessions:
EV Group - Evening Sessions Sponsor
Sponsor - Lunches:
Protavic - Event Sponsor
Sponsor - Refreshment Breaks:
MRSI - Break Sponsor
Sponsor - Refreshment Breaks:
i3 Electronics - Refreshment Break Sponsor
Sponsor - Refreshment Breaks:
ASM Pacific - Refreshment Break Sponsor
Sponsor - Mobile Charging Station:
Technic - Sponsor - Mobile Charging Station
Sponsor - Bag Insert/Giveaway:
Ubotic - Insert/Giveaway Sponsor
Sponsor - Bag Insert/Giveaway:
ALLVIA - Insert/Giveaway Sponsor
Sponsor - Bag Insert/Giveaway:
STATSChipPAC - Bag Insert/Giveaway Sponsor
sponsorships
available
   
Golf/Foundation Sponsors

"Eagle" Sponsor (3 holes):
DPC/GBC Premier Sponsor: VEECO

"Eagle" Sponsor (3 holes):
DPC/GBC Premier Sponsor: ASE US, Inc.

"Birdie" Sponsor (1 hole):

Golf Hole Sponsor: Amkor Technology
Hole Sponsor:
Hole Sponsor: NAMICS
Hole Sponsor:
Ubotic - Insert/Giveaway Sponsor
Hole Sponsor:
Golf Hole Sponsor: Coining Inc/Ametek
Hole Sponsor:
Golf Hole Sponsor: AGC Electronics America
Hole Sponsor:
ASM Pacific - Hole Sponsor

Hole Sponsor:
Golf Hole Sponsor: Infinite Graphics

5 hole sponsorships
available
   
Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: Semiconductor Packaging News
Media Sponsor: Chip Scale Review
Media Sponsor: MEPTEC
Media Sponsor: Webcom - Antenna Systems & Technology
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: Webcom - Thermal News
3D Incites - Media Sponsor



CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • GaN Systems
  • Honeywell
  • Indium
  • Isola Group
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NEO Tech
  • NGK NTK
  • Palomar
  • Plexus
  • Qualcomm
  • Specialty Coating Systems
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