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Professional Development Courses (PDCs)
For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 6th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 7:00pm in the foyer.
PDCs are available for a separate fee/registration from the full conference (Tuesday-Thursday registration). When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact email@example.com with questions..
|7:00 am - 7:00 pm||
|7:00 am - 8:00 am||
|8:00 am - 12:00 pm||
Morning Professional Development Courses (PDCs)
|PDC1:Introduction to Copper Pillar Flip Chip Interconnect
Course Leader: Mark Gerber, ASE US
PDC2: Fundamentals of Aligned Wafer Bonding
|PDC3: Trends & Analyses of Adv. Packaging Technologies and their Applications: from Smart Phones to Super Computers
Course Leader: Dev Gupta, APSTL, LLC
|PDC4: Polymers in Semiconductor Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
|10:00 am - 10:20 am||
|12:00 pm - 1:00 pm||
Lunch Only provided for those attendees registered for both Morning AND Afternoon PDCs
|1:00 pm - 5:00 pm||
Afternoon Professional Development Courses (PDCs)
|PDC5: Electrical Modeling & Test Strategies for 3D Packages
Course Leader: Bruce Kim, City University of New York
|PDC6: Fan Out Packaging - Technology Overview and Evolution
Course Leaders: John Hunt, ASE US
|PDC7: Emerging Challenges in Semiconductor Packaging
Course Leader: Raja Swaminathan, Intel
|PDC8: Stencil Printing Technology for Advanced Semiconductor and Assembly Applications
Course Leader: Phani Vallabhajosyula, Photo Stencil
|3:00 pm - 3:20 pm||
|5:00 pm - 7:00 pm|
Morning Professional Development Courses
8:00 am - Noon
Monday, March 6
This PDC course is an introduction to the Copper Pillar Flip Chip interconnect structure, process flows, materials and package integration process methods for evolving flip chip applications. Understanding the trade-offs between the traditional solder based flip chip and Copper Pillar is key in determining the silicon device layout and the type of design rules that can be leveraged. As part of this course, Copper Pillar structure formation will be reviewed as well as multiple Cu Pillar flip chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Process and equipment challenges associated with these processes and when will also be reviewed. Current market trends have led to additional questions regarding the longevity of flip chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.
Who Should Attend?
Anyone wanting to learn more about evolving Flip Chip related technologies including the basics and more about the process, material and structure options of Copper Pillar interconnect.
Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor's degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.
PDC3: Trends & Analyses of Advanced Packaging Technologies and their Applications: from Smart Phones to Super Computers
Course Leader: Dev Gupta, APSTL, LLC
Morning PDC: 8:00am – 12:00pm | $425 (Through 2/10/2017) - $475 (after 2/10/2017)
Increasing difficulty in pursuing Moore's Law combined with emerging applications like Machine Learning and IoT have brought about a wider interest in integration at the package level resulting in a bounty of Adv. Packaging technologies ranging from FO WLPs & SiPs to stacked dice interconnected with Through Silicon Vias (TSVs). In addition to traditional IDMs, now OSATs and even Foundries are now involved in Package development. To select appropriate Package from the wide selection available now and to predict future needs it is necessary that the Package User, Designer and even Developers and their Suppliers are able to compare these emerging Packages on the basis of not just mechanical attributes like form factor and I/O density but performance metrics and cost.
This unique course bridges the gap between courses that cover only the physical and mechanical attributes of packages and those that go into their electrical performance, cost, applications and roadmaps. We will start with an in depth description of Adv. Packaging technologies ranging from varieties of Flip Chip, FO WLPs & SiPs to 2.5 d stacked dice interconnected with Through Silicon Vias (TSVs), their typical applications that range from Smart Phones to Super Computers, key System requirements that guide their selection, as well as current implementations.
Status of novel features / processes associated with these new Adv. Packaging technologies e,g. micro Pillar Flip Chip technology, bond / debond wafers to carriers, TSVs will be briefly reviewed.
Next fundamentals of electrical performance e,g. signal integrity, losses in Packages, their dependence on interconnect & Package design and metrics e,g. Bandwidth, Power dissipation in typical computing systems will be outlined.
Based on above performance metrics we will discuss the latest applications of FO WLPs in Smart Phones, 2.5d modules and several types of GPUs and Servers incorporating versions of stacked Memory with TSVs. Next we will compare these emerging applications on the basis of their performance and packaging costs. Finally based on above we will speculate on some future directions for Adv. Packaging.
Who Should Attend?
This is an expanded version of a PDC offered at DPC for the last several years. Introductory descriptive material has been added w/o compromising depth. It would be of interest to Engineers, Managers and Analysts involved in Adv. Packaging.
Dr. Dev Gupta is the CTO at APSTL llc. Scottsdale, AZ, USA. At Motorola and Intel he pioneered and managed the discovery and implementation of many of the Adv. Packaging technologies that are industry standards today. These include electroplated solder and pillar bump flip chip technology, assembly robotics, Sn capped micro pillar technology including thermo compression flip chip bonding, organic substrates, the design of Fabs for their HVM, integrated microwave passives, industry first flip chip of Gallium Arsenide power devices etc, At APSTL he develops and licenses Adv. Packaging technologies as well as provides turnkey engineering & ramp of plants to manufacture them. At present he is involved in developing low cost approaches to high performance die stacks. He is a frequent speaker and instructor at Packaging Conferences.
This course will provide a broad overview of polymers and the important structure-property-process-performance relationships for electronic packaging. Topics to be covered are thermosetting polymers, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts). The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), underfills (capillary, pre-applied and wafer level), polymers for fan out wafer level packaging, substrate materials, and mold compounds. In most cases, adhesives, underfills, and mold compounds are applied as a viscous liquid and then cured. The flow properties are critical to performance in high volume manufacturing. The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, rheology changes during curing), underfills, and mold compounds.
Who Should Attend?
Packaging engineers and R&D professionals involved in product development, manufacturing and reliability testing of semiconductor packages would benefit from the course. Specific emphasis will be on the structure-property-processing-performance relationships in semiconductor packaging.
Dr. Jeff Gotro has over thirty years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He is an accomplished technology professional with demonstrated success solving complex polymer problems, directing new product development, and enabling clients to improve the financial impact of their polymer technologies. At InnoCentrix, Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. Jeff is an expert in thermosetting polymers used in electronic applications and has received invitations to present lectures and short courses at national technical conferences. He has published 60 technical papers (including 4 book chapters) in the field of polymeric materials for advanced electronic packaging applications, holds 15 issued US patents, and has 4 patent applications pending. In 2014 Jeff was awarded the IMAPS John Wagnon Technical Achievement Award and was named an IMAPS Fellow of the Society. Jeff has a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science and a B.S. in Mechanical Engineering/Materials Science from Marquette University.
Break: 10:00 am - 10:20 am
Afternoon Professional Development Courses
1:00 pm - 5:00 pm
Today’s miniaturization and performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid-arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use.
This course introduces comprehensive knowledge of electrical modeling and test solutions for 3D packages. We begin by a short tutorial on 3D packages including interposers and TSV. We then place particular emphasis on electrical modeling; test and debugging approaches for 3D packages for RF, bio, power and MEMS packages. Finally, we cover diagnosis and repair techniques for assembled packages.
Who Should Attend?
This course is beneficial to all design and test engineers, scientists, technical managers, design and manufacturing personnel, and production staffs in automotive, consumer, communication, computer, and aerospace industries. Although the course reviews most recent advances in 3D packaging, the course does not assume prior knowledge of these issues and hence is of interest for both experts and newcomers in this area.
Bruce Kim is a professor of the Department of Electrical Engineering at City University of New York. He has about 300 publications in packaging and testing areas. He has instructed previous PDCs at IMAPS, IEEE EPTC and ECTC conferences. He is a Fellow of IMAPS and received the IMAPS Outstanding Educator award in 2012. He has also been a student chapter advisor. His research interests are in 3D passive components modeling and testing.
Mobile electronics has created the need for ever increasing density and performance in electronics packaging with the advent of smart phones and the burgeoning Internet of Things. This evolution has led to a need for higher levels of component density and functionality than has been traditionally available using standard packaging. The packaging industry has responded with a plethora of packaging options, each tailored for a specific set of customer requirements.
We will review how the integration of a wide variety of wafer level processing technologies, substrate evolution and Flip Chip packaging structures have come together into what is being called Fan Out Packaging. These packages are for Mobile and server applications, and have higher levels of integration and sophistication than has ever been possible in the past. These options include Wafer Level Fan Out, Panel Level Fan Out with embedded die, and Chip Last Fan Out packaging. All of these can combine low cost materials and varied process flows to create both simple low density devices, and more complex System in Package and Package on Package applications. This course will provide an overview of the drivers, technology, advantages and disadvantages of various structural and processing options, as well as a view of potential future trends of Fan Out Packaging.
John Hunt is Senior Director for Engineering, Technical Promotion, at ASE (US) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan out Packaging Technologies at ASE. John has more than 40 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes, with a B.S. from Rutgers and an M.S. from University of Central Florida.
The course will introduce role of packaging in the interconnect hierarchy and introduce packaging trends per industry. We will then deep dive into the key elements driving the definition of a package architecture (scaling challenges, high speed signaling, power delivery, thermo-mechanical integration as well as thermal challenges). The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed. The second half of the course will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.
Who Should Attend?
The attendees are expected to have an in depth understanding of the fundamentals of packaging.
Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an ITRS author and iNEMI TWG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 18 patents and 23 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.
PDC8: Stencil Printing Technology for Advanced Semiconductor and Assembly Applications
Course Leader: Phani Vallabhajosyula, Photo Stencil
Afternoon PDC: 1:00pm – 5:00pm | $425 (Through 2/10/2017) - $475 (after 2/10/2017)
Stencils are used for printing flux, solder paste and inks for various assembly applications. This course will cover a wide variety of stencil printing applications including:
1- Significance of stencil printing, overview of stencil manufacturing and comparison
2- Stencil printing for wafer and substrate solder bumping applications.
3- Stencil Tools for wafer and substrate level ball drop.
4- Stencil printing for SMT / FC assembly.
5- Stencil printing on uneven substrate surfaces, including printing into deep cavities for embedded component packages.
Section 1 will review the significance of stencil printing in various applications. Details of stencil printing using various printers, various tooling needed and saving in production time will be discussed. This section also reviews the different parameters that need to be considered during stencil design, followed by discussion of various stencil manufacturing technologies and comparing the same in terms of print performance.
Section 2 will review stencil design requirements to achieve specific bump height after reflow. The bump height delivered depends on the volume of solder paste printed which depends on stencil thickness, aperture size, pad pitch, % paste transfer, and Area Ratio. This section will demonstrate how to achieve maximum bump height and bump height uniformity.
Section 3 will review stencil tool requirements for ball drop at the wafer-level. First flux is printed on the wafer with a normal single thickness stencil then a special step stencil tool with a stand-off on the wafer side is used to drop balls into the flux on each pad site on the wafer. Flux stencil and ball drop stencil tool design for ball sizes ranging from 250um down to 30um and pitches ranging from 400um down to 60um will be shown.
Section 4 will review stencil printing options for SMT / FC Assembly. Typically flux is printed for FC and solder paste for SMT. Two Print Stencil printing will be reviewed. Option A is to print flux 1st and paste 2nd with a relief pocket in 2nd stencil for printed flux. Option B is to print paste 1st and flux 2nd with a relief pocket in 2nd stencil for printed paste. Advantages of both options will be discussed.
Section 5 will review 3 Dimensional stencils for printing when the substrate has cavities for embedded FC on the substrate (printing into a lower surface on the PCB) and printing on the substrate having protrusions above the substrate such as mounted components. Reservoir printing into the cavities and special squeegee blades for printing around the protrusions will be discussed in detail.
Who Should Attend?
Engineers and managers responsible for advanced packaging development, package design and characterization in semiconductor, SMT, Optical (LED), automotive and aerospace industries. Both newcomers and experienced practitioners are welcome.
Phani Vallabhajosyula is the Director of Applications Engineering at Photo Stencil, a stencil manufacturing company in Golden, CO. The company is involved with producing for stencils for various FC and SMT applications since 1979. Dr.Vallabhajosyula leads the company’s R&D and provides advance printing solutions to the engineers from various semiconductor, LED and automotive industries. Prior to that she worked at Intel and was involved with substrate assembly process development as well as substrate design for various pathfinding platforms. She received her doctoral degree in materials science and engineering (Specialization in 3D printing) from the University of Texas at Austin, in 2011. She is currently a Senior member with IEEE, member of IMAPS, SMTA and serves as a reviewer for Rapid Prototyping Journal, Additive Manufacturing Journal and for Transactions on Component Packaging and Manufacturing Technology 2016.
Break: 3:00 pm - 3:20 pm
Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 7:00 pm
When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2.