Micross

14th International Conference and Exhibition on
DEVICE PACKAGING
www.imaps.org/devicepackaging

WekoPa Resort and Casino
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 6-8, 2018
Exhibition and Technology Showcase
March 6-7, 2018
Professional Development Courses
March 5, 2018
GBC Plenary Session
March 7, 2018
Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC

General Chair:
Peter Ramm
Fraunhofer EMFT Munich


General Chair-Elect:
Jon Aday
Qualcomm


Past General Chair:
Rozalia Beica
Dow Electronic Materials

Past General Chair:
Gilles Poupon
CEA




Professional Development Courses (PDCs)

 

Thank you to our Premier PLATINUM Sponsor:

Thank you to our Premier GOLD Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC

Thank you to our Premier SILVER Sponsors:

Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics Premier Silver Sponsor: Kyocera



TECHNICAL PROGRAM | FINAL PROGRAM PDF | SPEAKERS | PROFESSIONAL DEVELOPMENT COURSES (PDCs)
EXHIBIT DETAILS (SOLD OUT) | 2018 EXHIBITORS | 2018 Exhibit Floorplan
EXHIBIT/SPONSOR PROSPECTUS | GES EXHIBITOR "KIT"


OUR PDCs FEATURE A NEW 2-HOUR FORMAT THIS YEAR! For those wishing to broaden their knowledge of device packaging, a selection of 2-hour courses will be offered on Monday, March 5th, preceding the technical conference. Morning PDCs will run from 10:00am until 12:00 noon. Early afternoon PDCs will be held from 1:00pm until 3:00pm. Late afternoon PDCs will be held from 3:30pm until 5:30pm.The Welcome Reception will immediately follow the PDCs from 5:00pm until 7:00pm in the foyer.

PDCs are available for a separate fee/registration from the full conference (Tuesday-Thursday registration). When you register online for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of online registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact smoirano@imaps.org with questions.

 

7:00 am - 7:00 pm
Registration
 
**NEW 2-HOUR PDC FORMAT THIS YEAR**
2-HOUR COURSES - NEW TIMES/SCHEDULE
10:00 am - 12:00 pm
Morning Professional Development Courses (PDCs) - 10am-12pm

PDC1:Stencil Printing Technology for Bumping and Advanced Semiconductor Assembly Applications
COURSE CANCELLED

PDC2: Polymer Challenges in 2.5D and 3D Packaging
Course Leaders: Jeffrey Gotro, InnoCentrix, LLC

PDC3: The Science of Bond Testing
Course Leader: Bob Sykes, XYZTECbv

PDC4: Temporary Bonding of Electronics (Wafers, Packages, Displays)
Course Leader: John Moore, Daetec LLC

PDC5: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver
Course Leader: Mark Gerber, ASE US

12:00 pm - 1:00 pm
LUNCH - Only provided for those attendees registered for both Morning AND Afternoon PDCs
1:00 pm - 3:00 pm
Early Afternoon Professional Development Courses (PDCs) - 1pm-3pm

PDC6: Emerging Challenges in Semiconductor Packaging – Part 1 (Design)
Course Leader: Raja Swaminathan, Intel

PDC7: Fundamentals of 3D and 2.5D Packaging Integration
Course Leaders: Urmi Ray, STATS ChipPAC

PDC8: The Evolution of High Density Packaging
Course Leader: Phil Garrou, Microelectronic Consultants of NC

PDC9: Introduction to Solder Flip Chip with an Emphasis on Cu Pillars
Course Leader: Mark Gerber, ASE US

3:00 pm - 3:30 pm
BREAK
3:30 pm - 5:30 pm
Late Afternoon Professional Development Courses (PDCs) - 3:30pm-5:30pm

PDC10: Emerging Challenges in Semiconductor Packaging – Part 2 (Manufacturing)
Course Leader: Raja Swaminathan, Intel

PDC11: Manufacturing Failure Analysis and Test Strategies for TSV 3D Packages
Course Leaders: Bruce Kim, City University of New York

PDC12: MEMS and nanoMEMS Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology

PDC13: Fan Out Packaging Evolution & Complexity
Course Leader: John Hunt, ASE US

5:30 pm - 7:30 pm

Welcome Reception (All Attendees Are Invited To Attend)

Sponsored by:

Premier Platinum Sponsor: ASE US, Inc.

Premier Gold 
Sponsor - EMD Performance Materials

Premier Gold Sponsor - XYZTEC

Premier Silver Sponsor: Amkor Technology

Premier Silver Sponsor: NAMICS

Premier Silver Sponsor: Cadence

Premier Silver Sponsor: Mentor Graphics

Premier Silver Sponsor: Kyocera

 


***************
Morning Professional Development Courses
NEW TIME THIS YEAR -- 10:00 am - Noon
Monday, March 5

 

PDC1: Stencil Printing Technology for Bumping and Advanced Semiconductor Assembly Applications
COURSE CANCELLED
Morning PDC: 10:00am – 12:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
Stencils are used for printing flux, solder paste and inks for various assembly applications. This course will cover a wide variety of stencil printing applications including:

1- Significance of stencil printing, overview of stencil manufacturing and comparison
2- Stencil printing for wafer and substrate solder bumping applications.
3- Stencil Tools for wafer and substrate level ball drop.
4- Stencil printing for SMT / FC assembly - Step stencils and ultrathin stencils.
5- Stencil printing on uneven substrate surfaces, including printing into deep cavities for embedded component packages.

Section 1 will review the significance of stencil printing in various applications. Details of stencil printing using various printers, various tooling needed and saving in production time will be discussed. This section also reviews the different parameters that need to be considered during stencil design, followed by discussion of various stencil manufacturing technologies and comparing the same in terms of print performance.

Section 2 will review stencil design requirements to achieve specific bump height after reflow. The bump height delivered depends on the volume of solder paste printed which depends on stencil thickness, aperture size, pad pitch, % paste transfer, and Area Ratio. This section will demonstrate how to achieve maximum bump height and bump height uniformity.

Section 3 will review stencil tool requirements for ball drop at the wafer-level. First flux is printed on the wafer with a normal single thickness stencil then a special step stencil tool with a stand-off on the wafer side is used to drop balls into the flux on each pad site on the wafer. Flux stencil and ball drop stencil tool design for ball sizes ranging from 250um down to 30um and pitches ranging from 400um down to 60um will be shown.

Section 4 will review stencil printing options for SMT / FC Assembly. Typically flux is printed for FC and solder paste for SMT. Two Print Stencil printing will be reviewed. Option A is to print flux 1st and paste 2nd with a relief pocket in 2nd stencil for printed flux. Option B is to print paste 1st and flux 2nd with a relief pocket in 2nd stencil for printed paste. Advantages of both options will be discussed.

Section 5 will review 3 Dimensional stencils for printing when the substrate has cavities for embedded FC on the substrate (printing into a lower surface on the PCB) and printing on the substrate having protrusions above the substrate such as mounted components. Reservoir printing into the cavities and special squeegee blades for printing around the protrusions will be discussed in detail.

Who Should Attend?
Engineers and managers responsible for advanced packaging development, package design and characterization in semiconductor, SMT, Optical (LED), automotive and aerospace industries. Both newcomers and experienced practitioners are welcome.

Phani Vallabhajosyula is the Director of Applications Engineering at Photo Stencil, a stencil manufacturing company in Golden, CO. The company is involved with producing for stencils for various FC and SMT applications since 1979. Dr Vallabhajosyula leads the company’s R&D and provides advance printing solutions to the engineers from various semiconductor, LED and automotive industries. Prior to that she worked at Intel and was involved with substrate assembly process development as well as substrate design for various pathfinding platforms. She received her doctoral degree in materials science and engineering (Specialization in 3D printing) from the University of Texas at Austin, in 2011. She is currently a Senior member with IEEE, member of IMAPS, SMTA and serves as a reviewer for Rapid Prototyping Journal, Additive Manufacturing Journal and for Transactions on Component Packaging and Manufacturing Technology 2016.

PDC2: Polymer Challenges in 2.5D and 3D Packaging
Course Leaders: Jeffrey Gotro, InnoCentrix, LLC
Morning PDC: 10:00am – 12:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be: 1) learn how polymers are used in electronic packaging including die attach adhesives, underfills (capillary, no-flow and wafer level), mold compounds and substrate materials 2) gain insights on how polymers are used in Fan Out Wafer Level Packaging, 3) learn the key polymer challenges and processes for Fan Out Wafer Level Packaging, 4) understand rheology measurements and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Dr. Jeff Gotro has over thirty five years’ experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the American Chemical Society (ACS), the Institute for Management Consultants (IMC), Society of Plastics Engineers, the IEEE Electronic Packaging Society, and is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS). In 2014, Dr. Gotro received the John Wagnon Technical Achievement award from IMAPS. Jeff holds a Ph.D. in Materials Science with a specialty in polymer science from Northwestern University.

 

PDC3: The Science of Bond Testing
Course Leader: Bob Sykes, XYZTECbv
Morning PDC: 10:00am – 12:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
The success of the very latest developments in semiconductors and electronics, together with those that went before, depend on good and reliable bonds. Because of this the Bond Strength Tester has become an invaluable tool. Early tests were relatively simple but bond testing developed in line with the industry leading to the methods currently available. At the same time test standards were developed by individual manufacturers and consortiums with common interests. This development has up to now been an evolution. This meets most of what we think we need but lacks any common understanding of the fundamental objectives. The course is derived from decades of experience designing bond tests for the widest range of applications. It elevates bond testing to a science that takes you through the process of designing the optimum bond test for any process. For example, the course shows you how to decide if a pull test is better than a shear test, what speed to test at, what the best tool shape is. You may wonder why tests are done a certain way. The course will help you to both understand and challenge accepted practice. It is essential to anyone who relies on Bond Test data.

Who Should Attend?
Anyone who relies on Bond Test data, including, Package Designers, Production Engineers, Quality Assurance Managers.

A leading authority in Bond Testing Technology Bob Sykes is Chief Technical Officer for XYZTECbv located the Netherlands. In this position together with his previous position as the Technical Director for Dage Precision Industries he has gained worldwide recognition as an expert in the field of the development and design of bond testing equipment. His many achievements include: - Chief Designer of the Sigma and Dage 4000 ranges of Bond Testers; - Adviser to JEDEC on Bond Testing standards; - 7 granted company patents and many others pending; - Author and co-authored for many papers on the subject of Bond Testing; - Author and instigator of the “Science of Bond Testing” educational course. Bob has an Honours Degree in Mechanical Engineering, is a Chartered Engineer and Fellow of the Royal Institution of Mechanical Engineering. He has over 28 years experience in the Semiconductor and Electronics Industry.

PDC4: Temporary Bonding of Electronics (Wafers, Packages, Displays)
Course Leader: John Moore, Jared Pettit, Daetec LLC
Morning PDC: 10:00am – 12:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
Temporary bonding of electronic components is necessary to accurate completion of short processes as soldering or it span over several steps as thinning, lithography, plating or etching. These practices are used to process wafers, ceramics as HTCC/LTCC, laminates as SAR, ABF, or strip, and in creating displays. Adhering two precise materials requires several disciplines in chemistry and mechanical domains to achieve orientation, uniformity, and adhesion. Understanding these factors and controlling them during manufacturing is important for success. The choice of adhesive and de-bond technology will govern the type of carrier and process conditions (exposure to process chemicals, moisture, corrosives, etc.). The following topics will be discussed: diffusion de-bond (DDB), laser lift-off (LLO), thermal slide, flexible substrate peeling, wafer peel, surface contamination and cleaning, surface energy/contact angle, substrate physical-chemical condition, adhesive options, adhesion science, carrier designs (perforated & porous), measurements as: outgas, chemical & thermal resistance, TTV, adhesion, bondline, de-bonding, cleanliness.

The class will be an application-oriented tutorial that focuses on substrates, films, testing, adhesive films & tapes, coating and bonding adhesives, with applications of temporarily bonding to wafers, laminates, and displays/panels. Hands-on demonstrations include substrate bonding and measurement of adhesion force using materials with various tensile and elastic properties.

Who Should Attend?
Packaging scientists, engineers, managers, and others charged with responsibilities related to substrate or component bonding that is permanent or temporary.

Daetec’s engineering team conducts this class to facilitate a highly interactive "hands-on" setting. John Moore is technical director at Daetec, has co-authored many publications and patents in the area of coatings and cleaners. He, along with his team, hold degrees in chemistry of different disciplines. Their focus is on applications of coating, adhesion, and the effects of interfacial chemistry. John Moore is founder of Daetec, his third company, providing new products for the electronics market. In the last 15yrs, he has created some of the leading temporary bonding products for the industry. Mr. Moore performed his graduate work at UCSB in chemistry. Daetec is an internationally recognized company specializing in areas of temporary bonding and cleaning. For the past 15yrs, the company has created solutions for thin substrates down to 4um, encapsulating 300um bumps, or resisting temperatures to 450C. Daetec’s customers include top suppliers and fabs in microelectronics manufacturing.

PDC5: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver
Course Leader: Mark Gerber, ASE US, Inc.
Morning PDC: 10:00am – 12:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and overall package miniaturization. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. As SiP has evolved, there has also been interest in Fan Out Wafer level technology and the potential integration of multiple active devices as well as discretes into this technology- a brief overview of this option and considerations will be discussed.

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor’s degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

 

LUNCH : 12:00pm - 1:00pm
(Only provided for those attendees registered for BOTH Morning and Afternoon PDCs)

 

***************
EARLY Afternoon Professional Development Courses
NEW TIME THIS YEAR -- 1:00 pm - 3:00 pm

 

PDC6: Emerging Challenges in Semiconductor Packaging- Part 1 (Design)
Course Leaders: Raja Swaminathan, Intel
Early Afternoon PDC: 1:00pm – 3:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
The course will introduce role of packaging in the interconnect hierarchy and introduce packaging trends per industry. We will then deep dive into the key design elements driving the definition of a package architecture (scaling challenges, high speed signaling, power delivery). The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed.

Part 2 (PDC10 BELOW) will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

Who Should Attend?
The attendees are expected to have an in depth understanding of the fundamentals of packaging.

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an IEEE and ITRS roadmap author and iNEMI TWG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 26 patents and 28 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.

PDC7: Fundamentals of 3D and 2.5D Packaging Integration
Course Leader: Urmi Ray, STATS ChipPAC
Early Afternoon PDC: 1:00pm – 3:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
This course will cover the fundamental technology aspects of 3D and 2.5D integration including summaries of key benefits, process flow, test, cost and reliability challenges. The goal of this course is to provide a review of technology status to date and spend additional time on case studies of market and product adoption.

Course outline:

- Why 3D:
o New architectural & partitioning capabilities
o Package Density and Form Factor
o Improved Performance

- Types of 3D:
o Via first
o Via middle
o Via last

- Types of 2.5D
o Si/glass interposer
o Fan Out
o Laminate substrate/embedding

- Manufacturing process flow for Via-middle

- Manufacturing process flow for Si interposer

- Challenges for market adoption
o Cost
o Reliability
o Supply Chain
o Others

- Case Studies of successful recent product adoption
o HBM memory with TSV
o Graphics processor integration using 2.5D

- Roadmap

Urmi Ray is currently Senior Director at STATS ChipPAC focusing on advanced system in package (SIP) technologies. Prior to joining STATS, Urmi served as a Principal Engineer in Qualcomm where she had been the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in many aspects of advanced packaging technology area. She has a PhD from Columbia University (New York City).

PDC8: The Evolution of High Density Packaging
Course Leader: Phil Garrou, Microelectronic Consultants of NC
Early Afternoon PDC: 1:00pm – 3:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
1. Microelectronic Packaging Platforms
-Function & Early History of Packaging
-Peripheral Leaded packages
-Area array Packaging
-BGA packaging
-Bumping/ FC
-Redistribution, UBM, Underfill
-Wafer level Packaging (WLP)
-Copper pillar bump
-Embedded packaging ( molded fan out vs laminate embedded)
-Chips vs RDL first
-3D packaging (Stacked WB, Package on package, 3DIC)

2. Microelectronics Market & Business Considerations
-Markets and Applications
-The future of scaling
-Consolidation and Business Issues

3. Where is Packaging Technology Going

Dr. Philip Garrou retired from Dow Chemical in 2004 as Global Director of Technology for their Advanced Electronic Materials business unit. He is now contributing editor and blogger (“Insights from the Leading Edge”) for Solid State Technology , a subject matter expert (SME) for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP area.

PDC9: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Course Leader: Mark Gerber, ASE US, Inc.
Early Afternoon PDC: 1:00pm – 3:00pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
This PDC course is an introduction to the Copper Pillar Flip Chip interconnect structure, process flows, materials and package integration process methods for evolving flip chip applications. Understanding the trade-offs between the traditional solder based flip chip and Copper Pillar is key in determining the silicon device layout and the type of design rules that can be leveraged. As part of this course, Copper Pillar structure formation will be reviewed as well as multiple Cu Pillar flip chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Process and equipment challenges associated with these processes and when will also be reviewed. Current market trends have led to additional questions regarding the longevity of flip chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor’s degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

Break: 3:00 pm - 3:20 pm

***************
LATE Afternoon Professional Development Courses
NEW TIME THIS YEAR -- 3:30 pm - 5:30 pm

 

PDC10: Emerging Challenges in Semiconductor Packaging- Part 2 (Manufacturing)
Course Leaders: Raja Swaminathan, Intel
Late Afternoon PDC: 3:30pm – 5:30pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
Part 2 will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

Attendees are encouraged to attend Part 1 of this course (PDC6 ABOVE) so they get a holistic view of the Design challenges driving the Manufacturing challenges.

Who Should Attend?
The attendees are expected to have an in depth understanding of the fundamentals of packaging.

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an IEEE and ITRS roadmap author and iNEMI TWG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 26 patents and 28 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.

PDC11: Manufacturing Failure Analysis and Test Strategies for TSV 3D Packages
Course Leader: Bruce Kim, City University of New York
Late Afternoon PDC: 3:30pm – 5:30pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
This course introduces comprehensive knowledge of test solutions for 3D packages. We begin by a short tutorial on 3D packages including interposers and TSV. We then place particular emphasis on manufacturing failure analysis, test and debugging approaches for 3D packages for RF, bio, power and MEMS packages. Finally, we cover diagnosis and repair techniques for assembled packages.

Course Outline:
- Introduction to 3D package techniques
- 3D package modeling
- Electrical Test strategies
- TSV 3D package testing
- Manufacturing Failure Analysis
- Repair/diagnosis techniques for modules

Who Should Attend?
This course is beneficial to all design and test engineers, scientists, technical managers, design and manufacturing personnel, and production staffs in automotive, consumer, communication, computer, and aerospace industries. Although the course reviews most recent advances in 3D packaging, the course does not assume prior knowledge of these issues and hence is of interest for both experts and newcomers in this area.

Dr. Bruce Kim is a professor of the Department of Electrical Engineering at City University of New York. He has about 300 publications in packaging and testing areas. He has instructed previous PDCs at IEEE EPTC and ECTC conferences. He is a Fellow of IMAPS and received the Outstanding Educator award in 2012. He has also been a student chapter advisor. His research interests are in 3D passive components and testing.

PDC12: MEMS and nanoMEMS Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
Late Afternoon PDC: 3:30pm – 5:30pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
This course will provide a review of MEMS devices and explore futuristic concepts that combine MEMS and nanoscience. The merging of nanoscience and microelectromechanical systems presents an opportunity for development of next generation technologies for use in computers, wireless communication, biomedicine, and a variety of sensors.The course will start by providing an in-depth overview of the MEMS principles of operation, fabrication methods, and in particular the materials used in building MEMS structures. Variety of MEMS devices will be discussed while a particular emphasis will be placed on MEMS in wireless communication; and sensors and actuators used in industrial, medical, and automotive applications.

The introduction to nanoscience will start by evaluating how size can influence the properties of nanoscale systems. The nanomaterial synthesis and characterization methods will be explored next. The highly speculative discussion will offer a possibility for using nanoscale phenomena for technological purposes related to MEMS. The emphasis will be placed on merging the nanoscience with MEMS fabrication principles, design considerations, integration aspects, and packaging. In the third section, the packing and reliability of MEMS and nanoMEMS devices will be discussed. The integration of power supplies and energy storage devices with MEMS and nanoMEMS devices will also be covered. These devices will be the key in the packaging and for autonomous function of future devices.

Who Should Attend?
The course is open to anyone with general understanding of the physics, chemistry, and material science. The participants will have the opportunity to explore highly speculative, futuristic concepts and develop visionary views of the technological possibilities. The course is open to participants with no prior MEMS, nantotechnology, or power sources knowledge and would provide a reasonably broad general introduction into all three areas of technology.

Dr. Slobodan Petrovic is a professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, packaging Li batteries, sensor media compatibility, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 30 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 80 journal publications and conference proceedings; 2 book contributions and 35 pending or issued patents.

PDC13: Fan Out Packaging Evolution & Complexity
Course Leader: John Hunt, ASE US, Inc.
Late Afternoon PDC: 3:30pm – 5:30pm | $300 (Through 2/7/2018) - $400 (after 2/7/2018)

Course Description:
With the ubiquitous use of a wide variety of mobile devices, along with the rise of the Internet of Things, the Electronics industry has been driven by the need for a continual reduction in the size of semiconductor packaging. Fan Out technology has evolved as an alternative package in response to this need for miniaturization of electronics, while also providing improved electrical interconnectivity. At the same time, the wide use of mobile devices and the newer IOTs has driven the need for increased capability of data centers. Fan Out technology is finding value in the heterogeneous integration of die and memory with improved electrical performance for this application, with lower cost than traditional 2.5 packaging for these data center requirements.

We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into Fan Out Packaging. These packages are for both low and high density, with mobile and server applications. An overview of the concept of Fan Out packaging, a history of its evolution, low end and high end applications, and market trends will be included in this course.

Who Should Attend?
Anyone interested in the applicability of Fan Out technology to their packaging needs, or just interested in the latest capabilities of Fan Out packaging.

John Hunt is Senior Director, Engineering, Product Promotion, at ASE (US) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fanout Packaging Technologies at ASE. John has more than 40 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes, with a B.S. from Rutgers and an M.S. from University of Central Florida.

 

 

Welcome Reception (All Attendees Are Invited To Attend)
5:30 pm - 7:30 pm

Sponsored by:

Premier Platinum Sponsor: ASE US, Inc.

Premier Gold 
Sponsor - EMD Performance Materials

Premier Gold Sponsor - XYZTEC

Premier Silver Sponsor: Amkor Technology

Premier Silver Sponsor: NAMICS

Premier Silver Sponsor: Cadence

Premier Silver Sponsor: Mentor Graphics

Premier Silver Sponsor: Kyocera

 

 

 

Device Packaging Home

When you register online for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of online registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2.

 

 

 

Device Packaging Sponsorship (Need to be ahead of your competition? Join this list today!)

PLATINUM PREMIER SPONSOR

Premier Platinum Sponsor: ASE US, Inc.
GOLD PREMIER SPONSORS
Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
SILVER PREMIER SPONSORS
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics Premier Silver Sponsor: Kyocera
Corporate Sponsors
Corporate Sponsor - Dow Electronic Materials Corporate Sponsor - Technic
Mobile APP Sponsor: SETNA
SPTS - Corporate Sponsor
Corporate Sponsor - NGK NTK
Corporate Sponsor: Evatec
Corporate Sponsor: Applied Materials
Additional Event Sponsors

Mobile Station & Poster Session Sponsor: VEECO

Mobile Charging Station &
Poster Session Happy Hour

Poster Session Sponsor: SAMTEC

Poster Session Happy Hour

Break Sponsor - Intevac

Coffee Breaks (3)

Break Sponsor: 
TechSearch International

Coffee Break

Evening Panel & Reception Sponsor: Yield Engineering Systems, Inc.(YES)

Evening Panel & Reception

Break Sponsor: 
S3IP Binghamton University

Coffee Break

Sponsor: 
Kulicke and Soffa Industries

Bag Inserts & Web

 
Golf/Foundation Sponsors

"Birdie" Sponsor (1 hole):

DPC/GBC Premier Sponsor: ASE US, Inc.

Hole: 5 - Closest to Pin

"Birdie" Sponsor (1 hole):

EMD Performance Materials - Corporate Sponsor

Hole: 9 - Closest to Pin

"Birdie" Sponsor (1 hole):

Premier Gold Sponsor - XYZTEC

Hole: 15 - Closest to Pin

"Birdie" Sponsor (1 hole):

DPC/GBC Premier Sponsor: NAMICS

Hole: 12 - Longest Drive

"Birdie" Sponsor (1 hole):

Golf Hole Sponsor: Amkor Technology

Hole: 18 - Longest Putt

"Birdie" Sponsor (1 hole):

DPC Premier Gold Sponsor: Cadence

Hole: 1

"Birdie" Sponsor (1 hole):

Premier Silver Sponsor: Mentor Graphics

Hole: 2

"Birdie" Sponsor (1 hole):

Premier Silver Sponsor: Kyocera

Hole: 3

Golf Hole Sponsor: AGC Electronics America

Hole: 7 - Closest 2ND SHOT

Mobile Station & Poster Session Sponsor: VEECO

Hole: 6

Golf Sponsor: NxQ
Mask Aligners

Hole: 8

Golf Hole Sponsor: Nikon

Hole: 10

ASM Pacific - Hole Sponsor

Hole: 13

Corporate Sponsor - Technic

Hole: 14

Corporate Sponsor - Technic

Hole: 16

Golf Hole Sponsor: Advance Reproductions

Hole: 17

Golf Hole Sponsor: Dixon Golf

Hole: 4 - Straight Drive Competition
Hole: 11 - Hole-in-One Competition

Official Media Sponsors
3D Incites - Media Sponsor
Media Sponsor: Webcom - Electronics Protection
   



CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems