Device Packaging 2019

15th International Conference and Exhibition on
DEVICE PACKAGING
www.imaps.org/devicepackaging

WekoPa Resort
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 5-7, 2019
Exhibition and Technology Showcase
March 5-6, 2019
Professional Development Courses
March 4, 2019
GBC Plenary Session
March 6, 2019
Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC

General Chair:
Jon Aday
Illumina, Inc.


General Chair-Elect:
Rama Puligadda
Brewer Science


Past General Chair:
Peter Ramm
Fraunhofer EMFT Munich




Professional Development Courses (PDCs)

 

Thank you to our Premier PLATINUM Sponsor:

Thank you to our Premier GOLD Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group

Thank you to our Premier SILVER Sponsors:

Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas



REGISTER ONLINE | REGISTRATION INFO | HOTEL
TECHNICAL PROGRAM | PROFESSIONAL DEVELOPMENT COURSES (PDCs) | SPEAKER DETAILS
EXHIBITING COMPANIES | EXHIBITOR INFORMATION | EXHIBIT HALL FLOORPLAN
CHARITY GOLF OUTING


OUR PDCs FEATURE A 2-HOUR FORMAT AGAIN THIS YEAR! For those wishing to broaden their knowledge of device packaging, a selection of 2-hour courses will be offered on Monday, March 4th, preceding the technical conference. Morning PDCs will run from 10:00am until 12:00 noon. Early afternoon PDCs will be held from 1:00pm until 3:00pm. Late afternoon PDCs will be held from 3:30pm until 5:30pm.The Welcome Reception will immediately follow the PDCs from 5:30pm until 7:30pm in the foyer.

PDCs are available for a separate fee/registration from the full conference (Tuesday-Thursday registration). When you register online for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of online registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact smoirano@imaps.org with questions.

 

7:00 am - 7:00 pm
Registration
 
**2-HOUR PDC FORMAT THIS YEAR**
10:00 am - 12:00 pm
Morning Professional Development Courses (PDCs) - 10am-12pm

ROOM 103

PDC1: Introduction to Fan-Out Packaging
Course Leaders: John Hunt, ASE US, Inc.

ROOM 104

PDC2: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver
Course Leaders: Mark Gerber, ASE US, Inc.

ROOM 105

PDC3: Flip Chip Package Technology and Assembly Processes
Course Leader: Tom Dory, Fujifilm Electronics Materials

 

PDC4: Polymers Used in Wafer Level Packaging
CANCELLED

12:00 pm - 1:00 pm
LUNCH - Only provided for those attendees registered for both Morning AND Afternoon PDCs
1:00 pm - 3:00 pm
Early Afternoon Professional Development Courses (PDCs) - 1pm-3pm

ROOM 103

PDC5: Advances in Fan-Out Wafer Level Packaging (FOWLP)
Course Leader: Beth Keser, Intel Corporation

ROOM 104

PDC6: Fundamentals of 3D and 2.5D Packaging Integration
Course Leader: Urmi Ray

ROOM 105

PDC7: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Course Leaders: Mark Gerber, ASE US, Inc.

 

PDC8: MEMS and nanoMEMS Packaging
CANCELLED

3:00 pm - 3:30 pm
BREAK
3:30 pm - 5:30 pm
Late Afternoon Professional Development Courses (PDCs) - 3:30pm-5:30pm

ROOM 103

PDC9: Fan-Out Wafer/Panel-Level Packaging and 3D IC Heterogeneous Integration
Course Leader: John Lau, ASM Pacific Technology

ROOM 104

PDC10: Advanced Microelectronics Packaging
Course Leader: Phil Garrou, Microelectronic Consultants of NC

ROOM 105

PDC11: Introduction to Failure Analysis in Semiconductor Package Assembly
Course Leaders: Tom Dory, Fujifilm Electronics Materials

ROOM 106

PDC12: 5G/mmWave Package Development Requirements and Solutions
Course Leader: Urmi Ray

5:30 pm - 7:30 pm

Welcome Reception (All Attendees Are Invited To Attend)

Thank you to our Welcome Reception Premier Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas

 


***************
Morning Professional Development Courses
2-HOUR FORMAT -- 10:00 am - Noon
Monday, March 4

 

PDC1: Introduction to Fan Out Packaging
Course Leader: John Hunt, ASE US, Inc.
Morning PDC: 10:00am - 12:00pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)
ROOM 103

Course Description:
There are several factors driving packaging evolution in the electronics industry today. Mobile devices, along with the rise of the Internet of Things has driven the need for a continual reduction in the thickness and volume of semiconductor packaging. And, as the wafer node advancement has slowed, the value of heterogenous integration of multiple active and passive devices into more complex packaging has become apparent. What is needed now is the synergy of the reduction in size while at the same time the increase in complexity of new packaging technologies.

We will review how the integration of new wafer level processes and structures, substrate evolution and Flip Chip packaging have come together into what is being called Fan Out Packaging. These packages are for both low density and high density, both Mobile and server applications. They have higher levels of Homogeneous and Heterogeneous integration and sophistication than has ever been possible in the past. A basic description of the concept of Fan Out, a history of its evolution, and market trends will be included in this course.

John Hunt is Senior Director, Engineering, Technical Promotion, at ASE (US) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan Out Packaging Technologies at ASE. John has more than 45 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes. He has a B.S. from Rutgers and an M.S. from the University of Central Florida.

PDC2: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver
Course Leader: Mark Gerber, ASE US, Inc.
Morning PDC: 10:00am - 12:00pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)
ROOM 104

Course Description:
This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and overall package miniaturization. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. As SiP has evolved, there has also been interest in Fan Out Wafer level technology and the potential integration of multiple active devices as well as discretes into this technology- a brief overview of this option and considerations will be discussed.

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelors degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

PDC3: Flip Chip Package Technology and Assembly Processes
Course Leader: Tom Dory, Fujifilm Electronics Materials
Morning PDC: 10:00am - 12:00pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)
ROOM 105

Course Description:
The objective of this PDC is to provide an improved understanding of current flip chip package options and assembly flows. This workshop will begin with a discussion of current flip chip assembly including fanout wafer level packaging (FOWLP) and 2.5 & 3D package assembly. We will then discuss the newer technology options and issues. Flip chip packaging assembly is not new, but newer device requirement require more connections between the die and package, a tighter bump pitch and more functionally in the package. Laptop computers, tablets and smart phones, using flip chip packaging with thinned die and thin packages are driving new assembly requirements. All new technology drivers bring new challenges that will be discussed in this PDC. These assembly challenges include copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Also discussed are current wafer thinning process options including bonding and debonding to a carrier. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.

Dr. Thomas Dory has extensive experience in microelectronics covering semiconductor fab processing and assembly, hybrid circuits, and package assembly & test. Dr. Dory retired from Intel Corporation in the Assembly and Test Technology Development Research division after 20 years in R&D. As Pathfinding Integration Manager of the Intel Substrate Technology Research Labs, he was responsible for development of advanced packaging technology in the areas of MEMS including wafer level bonding, stacked die packages, and line pitch reduction designs. He specialized in packaging and assembly, focusing on high density substrate manufacturing, and chip assembly including flip chip and stacked die and 3D packaging. He was awarded ten patents while at Intel in the areas of embedded package capacitors, underfill applications, and package design. He currently is the R&D lab manager of Fujifilm Electronic Materials, USA.

PDC4: Polymers Used in Wafer Level Packaging
CANCELLED

 

 

LUNCH : 12:00pm - 1:00pm
(Only provided for those attendees registered for BOTH Morning and Afternoon PDCs)

 

***************
EARLY Afternoon Professional Development Courses
2-HOUR FORMAT -- 1:00 pm - 3:00 pm

 

PDC5: Advances in Fan-Out Wafer Level Packaging (FOWLP)
Course Leader: Beth Keser, Intel Corporation
Early Afternoon PDC: 1:00pm - 3:00pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)
ROOM 103

Course Description:
Now that Fan-out wafer level packaging (FO-WLP) has matured, unique advanced FO-WLP structures have been developed. This course will cover these advanced structures of FO-WLP and potential application spaces, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.

Beth Keser, Ph.D., a recognized global leader in the semiconductor packaging industry with over 20 years of experience, received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. from the University of Illinois at Urbana-Champaign. Beth's excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 28 patents and patents pending and over 40 publications in the semiconductor industry. Previously, Beth led Qualcomm's Fan-Out and Fan-In Wafer Level Packaging Technology Development and NPI Group for over 7 years where her team qualified over 50 products resulting in over 7 billion units shipped--technology consumers around the world enjoy in cell phones today. Based in Munich, Germany, Beth leads the Packaging & Systems Technology department in the Platform & Engineering Systems Group.

PDC6: Fundamentals of 3D and 2.5D Packaging Integration
Course Leaders: Urmi Ray
Early Afternoon PDC: 1:00pm - 3:00pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)

ROOM 104

Course Description:
- Why 3D:
o New architectural & partitioning capabilities
o Package Density and Form Factor
o Improved Performance

- Types of 3D:
o Via first
o Via middle
o Via last

- Types of 2.5D
o Si/glass interposer
o Fan Out
o Laminate substrate/embedding

- Manufacturing process flow for Via-middle

- Manufacturing process flow for Si interposer

- Challenges for market adoption
o Cost
o Reliability
o Supply Chain
o Others

- Case Studies of successful recent product adoption
o HBM memory with TSV
o Graphics processor integration using 2.5D

- Roadmap

Urmi Ray was most recently Senior Director at JCET Group focusing on advanced system in package (SIP) technologies. Prior to joining JCET Group, Urmi served as a Principal Engineer in Qualcomm where she had been the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in many aspects of advanced packaging technology area. She has a PhD from Columbia University (New York City).

PDC7: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Course Leader: Mark Gerber, ASE US, Inc.
Early Afternoon PDC: 1:00pm - 3:00pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)

ROOM 105

Course Description:
This PDC course will provide a historical overview and background on Solder Flip Chip technology with an emphasis on Copper Pillar Flip Chip as well as short market perspective. Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the traditional Solder based Flip Chip and Copper Pillar is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the Solder Bump and Copper Pillar Bump structure formation will be reviewed as well as multiple Cu Pillar Flip Chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions. Current market trends have led to additional questions regarding the longevity of Flip Chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelors degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

PDC8: MEMS and nanoMEMS packaging
CANCELLED

 
 

Break: 3:00 pm - 3:20 pm

***************
LATE Afternoon Professional Development Courses
2-HOUR FORMAT -- 3:30 pm - 5:30 pm

 

PDC9: Fan-Out Wafer/Panel-Level Packaging and 3D IC Heterogeneous Integration
Course Leader: John Lau, ASM Pacific Technology
Late Afternoon PDC: 3:30pm - 5:30pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)
ROOM 103

Course Description:
Because of the drive of Moore's law, SoC (system-on-chip) has been very popular in the past 10+ years. Unfortunately, the end of Moore's law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration contrasts with SoC. Heterogeneous integration uses packaging technology to integrate dissimilar chips with different functions into a system or subsystem. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost. Fan-out wafer-level packaging (FOWLP) has been getting lots of tractions since TSMC used their FOWLP to package the application processor for the iPhone 7. In this lecture, the following topics will be presented and discussed: (1) Formation of FOWLP: (a) Chip-first (die face-down); (b) Chip-first (die face-up); (c) Chip-last, (2) Fabrication of RDLs: (a) Polymer and ECD Cu + Etching; (b) PECVD and Cu damascene + CMP; (c) Hybrid RDLs, (3) TSMC InFO-WLP, InFO-PoP, InFO_AiP, (4) Formation of FOPLP: (a) PCB + SAP; (b) PCB + LDI; (c) PCB + TFT-LCD; (d) SEMCO PLP, (5) Wafer vs. Panel: (a) Application Ranges and (b) Critical issues of FOPLP, (6) Embedded Chips Panel-Level Packaging (ECP), (7) Embedded chips in silicon and glass, (8) Trends in FOWLP and FOPLP, (9) System-on-Chip (SoC), (10) Heterogeneous Integration vs. SoC, (11) Heterogeneous Integration on Organic Substrates (SiP), (12) Heterogeneous Integration on Silicon Substrates (TSV-Interposers), (13) Heterogeneous Integration on RDLs and/or TSV-less Interposers, (14) Samsung's Heterogeneous Integration on RDLs: (a) for Mobile Applications and (b) for high-end applications, and (15) Heterogeneous Integration Trends. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be explored.

John H. Lau has been a senior technical advisor of ASM since 2014 and a Senior Scientist/MTS at HP Lab/Agilent in California, US for more than 25 years. With more than 39 years of R&D and manufacturing experience in semiconductor packaging, he has published more than 480 peer-reviewed papers, 30 issued and pending US patents, and 19 textbooks on flip chip technologies, WLCSP, FOWLP, BGA, TSV for 3D integration, advanced MEMS packaging, lead-free solder and manufacturing, reliability of 2D and 3D IC interconnections.

PDC10: Advanced Microelectronics Packaging
Course Leaders: Phil Garrou, Microelectronic Consultants of NC
Late Afternoon PDC: 3:30pm - 5:30pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)

ROOM 104

Course Description:
1. Microelectronic Packaging Platforms
-Function & Early History of Packaging
-Peripheral Leaded packages
-Area array Packaging
-BGA packaging
-Bumping/ FC
-Redistribution, UBM, Underfill
-Wafer level Packaging (WLP)
-Copper pillar bump
-Embedded packaging (molded fan out vs laminate embedded)
-Chips vs RDL first
-3D packaging (Stacked WB, Package on package, 3DIC)

2. Microelectronics Market & Business Considerations
-Markets and Applications
-The future of scaling
-Consolidation and Business Issues

3. Where is Packaging Technology Going

Dr. Philip Garrou retired from Dow Chemical in 2004 as Global Director of Technology for their Advanced Electronic Materials business unit. He is now contributing editor and blogger (“Insights from the Leading Edge”) for Solid State Technology, a subject matter expert (SME) for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP area.

PDC11: Introduction to Failure Analysis in Semiconductor Package Assembly
Course Leader: Tom Dory, Fujifilm Electronics Materials
Late Afternoon PDC: 3:30pm - 5:30pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)

ROOM 105

Course Description:
PDC participants will receive an overview of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. Many process steps and controls are needed for a high yield and reliable assembly process. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Fault isolation, failure analysis, and materials analysis play a major role in the improvement of yield and reliability. Coordination of people from many disciplines is needed in order to achieve high yield and reliability. Each engineer needs to understand the impact of their choices and methods on the final product. This workshop will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.

Dr. Thomas Dory has extensive experience in microelectronics covering semiconductor fab processing and assembly, hybrid circuits, and package assembly & test. Dr. Dory retired from Intel Corporation in the Assembly and Test Technology Development Research division after 20 years in R&D. As Pathfinding Integration Manager of the Intel Substrate Technology Research Labs, he was responsible for development of advanced packaging technology in the areas of MEMS including wafer level bonding, stacked die packages, and line pitch reduction designs. He specialized in packaging and assembly, focusing on high density substrate manufacturing, and chip assembly including flip chip and stacked die and 3D packaging. He was awarded ten patents while at Intel in the areas of embedded package capacitors, underfill applications, and package design. He currently is the R&D lab manager of Fujifilm Electronic Materials, USA.

PDC12: 5G/mmWave Package Development Requirements and Solutions
Course Leader: Urmi Ray
Late Afternoon PDC: 3:30pm - 5:30pm | $325 (Through 2/1/2019) - $425 (after 2/1/2019)
ROOM 106

Course Description:
The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors. The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging. This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.

Urmi Ray was most recently Senior Director at JCET Group focusing on advanced system in package (SIP) technologies. Prior to joining JCET Group, Urmi served as a Principal Engineer in Qualcomm where she had been the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in many aspects of advanced packaging technology area. She has a PhD from Columbia University (New York City).

 

Welcome Reception (All Attendees Are Invited To Attend)
5:30 pm - 7:30 pm

Thank you to our Welcome Reception Premier Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas

 

 

 

Device Packaging Home

When you register online for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of online registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2.

 

 

 

Device Packaging Sponsorship (Need to be ahead of your competition? Join this list today!)

PLATINUM PREMIER SPONSOR

GOLD PREMIER SPONSORS
Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group
SILVER PREMIER SPONSORS
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas
Corporate Sponsors
Corporate Sponsor - NGK NTK
Corporate Sponsor - DuPont Electronics & Imaging
SPTS - Corporate Sponsor
Mobile APP Sponsor: SETNA
MacDermid Alpha Electronics Solutions - Corporate Sponsor
Corporate Sponsor - Technic
Corporate Sponsor: Pac Tech
Corporate Sponsor: Evatec
Corporate Sponsor: Applied Materials
Additional Event Sponsors

Break Sponsor: Metalor

Coffee Break

Exhibit Reception Sponsor: JX Nippon Mining & Metals

Exhibit Reception

Notebook Sponsor: SMART Microsystems

Session Notebooks/Pens

 
Golf/Foundation Sponsors

"Birdie" Sponsor:

DPC/GBC Premier Sponsor: ASE US, Inc.

Hole: 5 - Closest to Pin

"Birdie" Sponsor:

EMD Performance Materials - Corporate Sponsor

Hole: 9 - Closest to Pin

"Birdie" Sponsor:

Premier Gold Sponsor - XYZTEC

Hole: 15 - Closest to Pin

"Birdie" Sponsor:

Premier Gold Sponsor - JCET Group

Hole: 7 - Closest 2ND SHOT

"Birdie" Sponsor:

Golf Hole Sponsor: Amkor Technology

Hole: 18 - Longest Putt

"Birdie" Sponsor:

DPC/GBC Premier Sponsor: NAMICS

Hole: 12 - Longest Drive

"Birdie" Sponsor:

DPC Premier Gold Sponsor: Cadence

Hole: 1

"Birdie" Sponsor (1 hole):

Premier Silver Sponsor: Mentor Graphics

Hole: 2

"Birdie" Sponsor:

Premier Silver Sponsor: Xperi / Invensas

Hole: 3

ASM Pacific - Hole Sponsor

Hole: 13

Golf Hole Sponsor: Advance Reproductions

Hole: 6

Golf Sponsor: NxQ
Mask Aligners

Hole: 8

Golf Hole Sponsor: Nikon

Hole: 10

Exhibit Reception Sponsor: JX Nippon Mining & Metals

Hole: 14

Golf Sponsor - Kite Rocket

Hole: 16

Golf Sponsor - SUSS Microtec

Hole: 17

Golf Hole Sponsor: Dixon Golf

Hole: 4 - Straight Drive Competition
Hole: 11 - Hole-in-One Competition

Official Media Sponsors
3D Incites - Media Sponsor
Media Sponsor: MEPTEC
   



CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic