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Field	Abstract	Abstract Text
Abstract No:	10ai001	For the majority of wafer-level 3D integration or TSV integration, full wafers of a specific function (e.g., processors, DSPs, SRAM, DRAM, and embedded wireless network) are produced separately and then stacked vertically via chip-to-wafer or wafer-to-wafer bonding in order to create a multi-functional device. All envisioned process flows for 3D integration on wafer level contain wafer bonding as a key step. Over the last two decades, various bonding methods have been developed and implemented for volume production. Due mainly to the thermal budget issue of CMOS devices, bonding processes compatible with CMOS processing are limited to metal bonding (Cu-Cu or Cu-solder-Cu), low-temperature direct oxide bonding, polymer adhesive bonding, and several hybrids of those methods. Patterned metal thermo-compression bonding is one of the most explored bonding methods for TSV integration because it can facilitate fine-pitch, high-density stacking of various devices leading to lower electrical resistance and higher mechanical strength. One of the major advantages of direct oxide bonding method is that pre-bonding (i.e., wafer contact and hydrogen bonds formation) occurs at room temperature, so a run-out error in alignment can not be induced during bonding and thus the achievable post-bond alignment accuracy is better than that with any high temperature bonding methods. The main advantages of adhesive bonding include the low bonding temperature (200 – 300 °C depending upon polymer materials) compared to metal bonding, the tolerance to the topography or conditions of wafer surfaces, the compatibility with standard CMOS wafers, and the ability to join any wafer materials. All details in unique characteristics of those three bonding methods, such as advantages and demerits of each process, post-bond alignment accuracy, process time, and throughput, will be presented at the conference.
Event:	AIT_2010
Paper Title:	Advances in Wafer Bonding Techniques Enabling Vertical Integration
Author:	Bioh Kim
Author's Company:	EV Group
Job Title:	Global Business Development Manager
Phone:	480-294-9342
City:	Tempe
State:	AZ
Country	USA
Email:	b.kim@evgroup.com
Keywords:	TSV integration chip-to-wafer bonding wafer-to-wafer bonding

Field	Abstract	Abstract Text
Abstract No:	10ai002	High performance devices must sustain large currents at elevated temperatures for extended periods of time. High current density and operating temperatures have a detrimental impact on electromigration performance of a semiconductor package because they accelerate the metal diffusion and the dissolution of the Under Bump Metallization (UBM) into the solder bump causing a failure. In this work, we investigate the electromigration performance of Pb-free µPILR™ interconnects within fine-pitch flip-chip packages. For package level testing, we used a test vehicle with more than 10,000 interconnects on 18x20x0.75mm die packaged on a 40x40x1.19mm substrate. The chip has 0.090mm diameter Sn/2.5Ag solder bumps with a minimum pitch of 0.150mm and maximum pitch of 0.200mm. The packages were tested under different current densities including 37.7kA/cm2 and 45.2kA/cm2 at 125°C and 150°C. The failure analysis reveals 100% failures due to depletion of the Cu UBM along with excessive voiding on the die-side with electrons moving from die to substrate. Voids initiated at the Cu6Sn5-solder interface with large void formation near Cu3Sn-Cu6Sn5 interface. No substrate-side damage was observed in this multi-pair daisy chain structure irrespective of the current direction. A mean time to failure of >4500hrs measured for packages tested at a current density of 45.2kA/cm2 at 125°C. The enhanced electromigration performance is due to the Inter-Metallic Compound formation around the Cu pin on the substrate coupled with the reduction in the solder joint resistance from the unique shape of the µPILR interconnects. In conclusion, this work will discuss a fine-pitch µPILR™ interconnect technology that offers superior electromigration performance and a significant lifetime improvement with delayed electromigration induced failures. The enhanced electromigration performance of the µPILR interconnect combined with other reliability benefits make it an excellent alternative to conventional solder joints with thin film stack UBMs, thicker copper UBM or tall copper post on die.
Event:	AIT_2010
Paper Title:	Electromigration Performance of Fine-pitch µPILR™ Interconnects in Flip Chip
Author:	Rajesh Katkar
Author's Company:	Tessera Inc.
Job Title:	Sr. Product Engineer
Phone:	408-321-6082
City:	San Jose
State:	CA
Country	USA
Email:	rkatkar@tessera.com
Keywords:	Electromigration Flip Chip Pb-free

Field	Abstract	Abstract Text
Abstract No:	10ai003	As the industry implements 3D Integration, the push to smaller pitches will be driven by the demand for I/O and P/G compatibility. At the same time, the market wants a time to market less than or equal to 6 months. To meet these market factors, the most reasonable approach is to adopt current assembly and packaging approaches with process modifications directed to minimize line and space dimensions. One demonstrated technology is that of dispensable 3D Interconnects using hybrid jetting techniques. That technology has been further extended to sub-70 um pitches by adopting aerosol jetting techniques. The benefits of these dispensable 3D interconnects are the minimum length of metallization, reduction in the inductance, minimum stress on the assembled stacks while not taking valuable Silicon real estate. This paper will review this aerosol jetting technology for 3D Integration. Control of the line quality including line height, width, and line edge roughness is possible with relative atomization flows and pressures leading to Cpk well over 1. Ink interactions will be studied including ink temperature and viscosity effects. Finally, the technology has also been scaled up to high volume manufacturing and results will be reviewed.
Event:	AIT_2010
Paper Title:	Sub-70 um Dispensable Inteconnects for 3D System-In-Package Assemblies
Author:	Suzette K. Pangrle
Author's Company:	Vertical Circuits, Inc.
Job Title:	Principal Scientist
Phone:	831-438-3887 x132
City:	Scotts Valley
State:	CA
Country	USA
Email:	suzette.pangrle@verticalcircuits.com
Keywords:	3D Interconnects SIP Fine Particle Ink

Field	Abstract	Abstract Text
Abstract No:	10ai005	Optomec's Aerosol Jet print platform provides an evolutionary alternative to both wire bond and TSV technology, providing a high density 3-dimensional interconnect solution that enables multi-functional integrated circuits to be stacked and vertically interconnected in high performance Multi-Chip Packages (MCP's). The die stacks can include up to 8 die, with a total stack height below 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Closely coupled pneumatic atomizers with multiplexed print nozzles are used to achieve production throughputs of greater than two interconnects per second per nozzle. The Aerosol Jet deposits silver nanoparticle ink connections on staggered multi-chip die stacks. High aspect ratio interconnects with <30-micron line width and 6-micron line heights have been demonstrated at sub 75-micron pitches with resistivity <1x10^-7 ohm*m. Pre-production yields exceeding 80% have been consistently realized. This paper will be further expanded to include final production packaging and results of the fully integrated Aerosol Jet print platform.
Event:	AIT_2010
Paper Title:	Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications
Author:	Michael O'Reilly
Author's Company:	Optomec, Inc.
Job Title:	Product Management
Phone:	978-500-3431
City:	Albuquerque
State:	NM
Country	USA
Email:	moreilly@optomec.com
Keywords:	3D Interconnects Printed Electronics Wire Bond Replacement

Field	Abstract	Abstract Text
Abstract No:	10ai007	Optical waveguides based on organic materials have been fabricated in a laboratory environment but the scaling and manufacturing processes needed to produce these waveguides have been scant. The volume production of low loss organic waveguides in a conventional state of the art PWB manufacturing plant is explored by the authors and the results are presented in this paper. The emphasis of our work is in developing scalable processes to produce high yield and low cost organic optical waveguide in a manufacturing environment. In this paper, we will show various organic optical waveguide samples using the fabrication methods developed in our facility. Discussion of the processes, materials and equipment sets that are employed in the fabrication of the organic optical waveguides will be presented. The preparation of substrates to be used as the base for waveguide build up layers is described. The requirements of clean room processing steps for the subsequent fabrication of optical layers will be explained. Rational of fabrication tool set and process selection will be discussed. Loss measurement test equipments and test strategy of organic optical waveguides will also be described. Finally, waveguide reliability and loss measurement results will be presented.
Event:	AIT_2010
Paper Title:	Optical Interconnect Using Optopolymer Material
Author:	How Lin
Author's Company:	Endicott Interconnect Technologies, Inc.
Job Title:	Chief Scientist
Phone:	607-755-5842
City:	Endicott
State:	NY
Country	USA
Email:	How.Lin@eitny.com
Keywords:	OPTICAL INTERCONNECT OPTOPOLYMER organic optical waveguide

Field	Abstract	Abstract Text
Abstract No:	10ai006	With the advancement of electronic industry, IC component becomes miniaturized; pitch size gets smaller and I/O number gets more and more. In addition to these, lead-free soldering process has to be implemented due to law requirements. However, there are some reliability issues such as poor process yield, weak mechanical strength of solder joint, and poor thermal cycling performance. A few methods that have been or will be implemented include capillary underfill, corner bond, no-flow underfill, underfilm and wafer-level underfill process. All the processes are encountered with unsatisfied process yield, reliability scarification, lengthy application process and so on. In order to resolve these issues we have successfully developed a first individual solder joint encapsulant adhesive. The first individual solder joint encapsulant adhesives-SMT256/266 are applied by printing or dipping process onto a substrate or component, SMT256 can remove metal oxide from pads and bumps to allow solder joint formed, then cure with the formation of 3-D polymer network encapsulating each individual solder joint, in-between solder joints there are no adhesives blocking outgassing channel to ensure process yield. After being used in the customer field for a few years, the implementation of SMT256 can improve the process yield, eliminating voids and crack in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT256 is high up to 6000 cycles, at least 4000 - 5000 cycles higher than other process. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our presentation.
Event:	AIT_2010
Paper Title:	A First Individual Solder Joint Encapsulant Adhesive
Author:	Wusheng Yin
Author's Company:	YINCAE Advanced Materials, LLC
Job Title:
Phone:	315-849-3671
City:	Rome
State:	NY
Country	USA
Email:	wyin@yincae.com
Keywords:	solder joint encapsulant adhesives lead-free soldering SMT256/266

Field	Abstract	Abstract Text
Abstract No:	10ai004	Electronic manufacturers are continually striving to decrease costs and increase functionality of electronic devices and components. Directly printing electronic circuitry onto low-cost substrates, or onto packages, is proving to be an excellent technique for high speed, low cost manufacturing of circuits and devices and is rapidly growing into a multi-billion dollar industry. However, the growth of this industry depends on the availability of suitable inks. In this paper we present details of a new family of nano silver-based conductive inks that NanoMas has developed for the printed electronics industry, and detail the use of these inks in several applications. The inks that we have developed are based on 5nm silver particles that we manufacture. The particles are fabricated using a low cost, readily scalable, wet chemistry process. The small size of the particles results in the inks exhibiting sintering temperatures below 100˚C, facilitating the printing of conductive traces on most common polymer substrates. Using these particles we have fabricated inks for a wide range of printing techniques including ink-jet, gravure, and screen, and aerosol printing. After sintering the printed materials exhibit resistivities as low as 2-5µOhm.cm. In this presentation we describe the use of our silver-base inks to fabricate conductive traces for packaging and flex-circuit applications. In particular we will detail the use of nano silver -based inks to fabricate high density three-dimensional interconnect solutions using aerosol printing. We also describe the use of the formulated inks to fabricate conductive traces several microns thick using ink-jet printing. For both of these applications we demonstrate that using low sintering temperatures the printed traces exhibited the required low electrical resistivities and high adhesion to a variety of substrate materials, and that the processes deliver the high throughput, and narrow trace widths and controlled thicknesses that printed electronics require.
Event:	AIT_2010
Paper Title:	Printing Conductive Traces using Nano Silver-Based Inks
Author:	David Van Heerden
Author's Company:	NanoMas Technologies
Job Title:	Principal Applications Engineer
Phone:	443-610-3288
City:	Endicott
State:	NY
Country	USA
Email:	David.vanheerden@nanomastech.com
Keywords:	Conductive Inks Printed Electronics Electronic Packaging

Field	Abstract	Abstract Text
Abstract No:	11ait008	This paper discusses how to choose the optimum ultrasonic frequency for wirebonding thin gold or aluminum and heavy aluminum wires or ribbons. For different surface properties, wire thicknesses and bond pad parameters, it appears that no single US frequency is ideally suited. Rather, the main strategy we found is to use as high an US frequency as possible and as low as necessary, bearing in mind that at higher frequencies the parameter windows become considerably narrower.
Event:	AIT_2011
Paper Title:	Which US Frequency is Best for Wirebonding?
Author:	Josef Sedlmair
Author's Company:	F&K Delvotec Bondtechnik GmbH
Job Title:
Phone:	+498962995142
City:	Ottobrunn, Munich D-85521
State:
Country	Germany
Email:	josef.sedlmair@de.fkdelvotec.com
Keywords:	Wirebonding Ultrasonic Frequency Optimization

Field	Abstract	Abstract Text
Abstract No:	11ait001	Package environment influence critically the radio frequency integrated circuit (RFIC) performances. The old design approach which emphasises only on mechanical and thermal sides with disregards of electromagnetic phenomena happening inside packages, at high frequencies, makes the RFICs unusable. In fact, commercial use of high frequency spectrum has been extensively increased during the two last decades (WLAN: 2.4 and 5 GHz, UWB: 3-10 GHz, and DBS: 11-12 GHz) due to the massive demand on high frequency integrated circuits for civilian and military applications. This has given increasing interest and attention to RF packaging industry. An ideal RF electronic package must keep the RFIC inputs and outputs unchangeable in term of their functionalities. However the package material medium, ambient temperature and conventional methods of interconnecting chips to package alter hard the RFIC performances. Recently, researchers and engineers have carried investigations mainly on the interconnection techniques to find appropriate solutions for signal integrity, cross talk and phase delay problems, whereas little or no attention has been received by package leads design to improve RF package performances. For some microwave components such as phase shifters integrated circuits, the phase shifting cause by actual package design affect considerably their performances which limits the use of wire or ribbon bonding approaches as interconnection techniques for this case of RFICs. Moreover, the lead's metallic mass of some popular package used in RF packaging such as quad flat non-lead (QFN) introduces a non-neglected parasitic inductance which is responsible for interconnection phase shifting phenomena. In this work we propose a novel technique for QFN leads design to remedy the problem of phase shift. This technique can compensate the effect of transmission line inductance and, hence, reduces the related amount of the considered transmission line phase shift caused by other electrical interconnections as has been shown by simulated results.
Event:	AIT_2011
Paper Title:	Investigations on RF Lead for High Frequency QFN Package Applications
Author:	Mohssin Aoutoul
Author's Company:	MAScIR Micro
Job Title:	Researcher
Phone:	+21-253-801-4161
City:	Sala Al Jadida, Rabat 11100
State:
Country	Morocco
Email:	m.aoutoul@mascir.com
Keywords:	High Frequency interconnection QFN package

Field	Abstract	Abstract Text
Abstract No:	11ait006	Tremendous interest over direct copper pillar bonding is evident for advanced interconnects in high density electronic devices such as three-dimensional integrated chips/packages. Such demand is primarily driven by its inherently superior mechanical, electrical and reliability performance and low material cost as compared to gold. Despite the increasing role of copper in advanced packages, one key consideration has to be overcome, that is the need for high thermal bonding due to the oxidative nature of copper. Generally, ultrahigh vacuum environment and harsh bonding conditions in particularly high bonding temperature (≥300°C) are required in order to achieve strong Cu to Cu joints. Though other alternatives such as capping the copper pillar with solder helps to reduce the bonding temperature required due to eutectic bonding, long term reliability issues due to brittle intermetallic formation was inevitable. We had previously reported an alternative approach of applying an organic monolayer on copper surfaces in enabling direct copper bonding at a much lower temperature (≤100°C) and in ambient. Our studies revealed that the layer passivates and protects the copper surface against oxidation prior to bonding. While so, it is also critical that the joints' electrical and reliability performance are not compromised due to the use of the organic material. In this study, we demonstrate strong metallurgical bonding using coated copper micropillars under ambient condition. Reliable mechanical joint integrity of bond strength 30 MPa was achieved even at low bonding temperatures ranging from 100°C – 250°C. The average electrical resistance of direct Cu-Cu bonds is found to be as low as 5 mΩ. High temperature storage test according to JEDEC standard demonstrated long term reliability performance where electrical conductivity was maintained. It is apparent that despite the possibility of fragmented organic constituents being left within the bonded joints after bonding, the reliability performance of such direct copper joints can be maintained.
Event:	AIT_2011
Paper Title:	Reliable Direct Copper Interconnects using Low Temperature Bonding with Organic Monolayers
Author:	Ang Xiao Fang
Author's Company:	Singapore Institute of Manufacturing Technology
Job Title:
Phone:	+(65) 6793-8981
City:	Singapore 638075
State:
Country	Singapore
Email:	xfang@SIMTech.a-star.edu.sg
Keywords:	copper organic monolayers reliability

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