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Wafer Level Chip Size Packaging Technology Enables Miniaturization of Automotive Electronics
Keywords: Miniaturization, Automotive Electronics , Wafer-Level Chip-Size Packaging
The use of solid state image sensors to build inexpensive digital cameras for automotive applications has been gaining momentum in the last two years. Applications include detecting movement of nearby pedestrians, adjusting deployment of airbags to the exact location and physical characteristics of all passengers in the car, and enabling “hands-free” parking. Incorporating image sensors in automotive applications elevates the reliability requirements for the camera module when compared to the consumer market. The camera module is required to perform in harsh environmental conditions without any degradation in the performance of the image sensor. The ramifications of failure in automotive applications are much more significant than in conventional camera applications. In order to comply with these harsh requirements, the image sensor must be packaged in a way that will protect it from humidity and temperature changes while keeping the optical performance intact. One of the more common packaging technologies used today in automotive applications is the ceramic leadless chip carrier (CLCC). This has been popular because the ceramic package protects the sensor from harsh environmental conditions. However, using this technology significantly increases the overall dimensions of the camera module without providing any cost benefits to the manufacturer. The author will present a new wafer-level chip-size packaging technology compatible with automotive requirements. With this technology, the image sensor is protected from contamination using a cover glass from the initial stage of processing. The electrical contacts are then routed to the back side of the silicon to solder bumps, thus making it suitable for standard surface mount technology (SMT) assembly. Being a true chip-size technology, the packaged die is the same size as the original die. The thickness of the packaged die is significantly reduced in this technology, as well, with the final thickness being approximately half the thickness of the original silicon. This in turn allows the distance between the image sensor and the assembly board to be shorter, thus reducing the overall camera module size further. In addition, as all packaging processes are performed at the wafer level, this approach enables cost benefits from the economies of scale of wafer-level processing. The reduction in package size in both the lateral and vertical directions, the high reliability, and the economies of scale of wafer-level processing make this technology an excellent option for image sensors in automotive applications.
Giles Humpston, Director R&D
Tessera Inc.
San Jose, CA

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