Here is the abstract you requested from the CICMT_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Comparison of IBM PowerPC Processors in High Speed Multi Layer Ceramic Packages: Ceramic Designs and Influence of Wiring Layout|
|Keywords: Glass ceramic, LTCC, Copper interconnect|
|IBM’s High Performance Glass Ceramic (HPGC) LTCC modules are predominantly used in high end server applications for extreme reliability and performance requirements. As the semiconductor industry progresses to fragile ultra low K dielectrics, higher power density requirements necessitating a stable thermomechanical substrate and higher frequencies ceramic packaging has demonstrated its longevity. As a baseline for performance comparisons between different ceramic packages, a single die configuration based on IBM’s PowerPC architecture was used to characterize the substrate using net DC resistance and low frequency impedance measurements. Using these die a set of modules were built from each substrate type and a full standard and overclocked deck level and board level characterization over a range of temperatures and voltages was performed. Die lots were selected based on their IDDQ to ensure a common chip level comparison. Packages included: IBM’s alumina ceramic using molybdenum wiring; IBM’s HPGC ceramic using copper wiring; and competitive packages using either tungsten or copper wiring that were used to derive a baseline performance comparison. Voltages from 1.0V to 1.4V were used to determine the full performance response of the die. The results show a clear trend towards the improvement in Fmax stability during overclocking due to lower package DC resistance.|
|Dr. Christopher Spring, High-Speed RF Applications Engineer
Hopewell Junction, NY