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Chip Embedding by Chip in Polymer Technology
Keywords: die bonding, embedded chips, laser drilling
The functional density of electronic systems is unfailingly increasing and is expected to continue so at least within the predictable future. In electronic packaging technology strategies for densification are, however, not as streamlined as in semiconductor industries. The paper describes a technology for the realization of packages and System-in-Packages (SIP) with embedded components. Embedding of semiconductor chips into substrates has several advantages. At first it allows a very high degree of miniaturization, since multiple layers of embedded components can be sequentially stacked. A further advantage is the beneficial electrical performance by short and geometrically well controlled interconnects. Furthermore the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability. In the EU funded project HIDING DIES industrial and academic partners are combining their expertise to achieve stable technology platforms for highest integration. The technology for component embedding, called “Chip in Polymer“, will be described. This technology uses thin chips which are die bonded and embedded by vacuum lamination of Resin Coated Copper (RCC) layers. The electrical contacts are made by laser drilling and Cu metallization. As the result chips are fully integrated in a flat substrate. Further layers can be applied or other components can be conventionally assembled on top. The process technology will be described in detail. The realization of different test vehicles will be discussed and as an example the embedding of a Chip Card controller IC, into a 4-layer PCB structure with a total thickness of 300 µm will be presented. The chip has a size of 2.4x2.4 mm˛, a thickness of 50 µm and 8 I/Os. The effect of different lamination parameters on the chip will be discussed. The investigation has shown, that inappropriate lamination can result in chip cracking. Reliability investigations of embedded chips were performed. For all tests, thermal storage, humidity storage, thermal cycling and moisture level sensitivity, the devices have shown an excellent reliability. Since the embedding technology does not have classical failure modes like solder fatigue, the new failure mechanisms will be discussed briefly.
Lars Boettcher, R&D Engineer
Fraunhofer Institute for Reliability and Microintegration (IZM) Berlin
D-13355 Berlin,
Germany


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