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Power Integrity: Design Methodology for Chip-Package-PCB Co-Design
Keywords: Power Integrity, Power Delivery Network, Printed Circuit Board
This paper demonstrates a Chip-Package-PCB Co-Design Methodology for Power Integrity. An example flow for power integrity simulation is shown that can be applied to complex electronic systems. Points of focus include 3D extraction for use with buffer models for analysis of core and IO power, including simultaneous switching output (SSO) noise. Examples illustrate the appropriate steps involved with extracting and simulating signal nets together with the full PDN. Consideration of fundamental design options, including number, value and location of decoupling capacitors, and the number of power/ground/signal planes will be illustrated.
Michael Brenneman, Technical Director, Packaging & PCB
Ansoft Corporation
San Jose, CA

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