Here is the abstract you requested from the DPC_2007_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|System In Package (SiP) and Stacked Package Solutions|
|Keywords: System in Package, Package on Package, Electromagnetic Extraction|
|Faster switching, higher pin count, lower supply voltages, and the need for greater density are placing new demands on signal and power integrity. While BGA and flip-chip package solutions are already widely deployed, next generation designs are targeting System In Package, stacked package solutions, and SOC to meet future demanding performance goals. This paper discusses the challenges with advanced package design and highlights a new approach to design and verify performance of the package, board, and circuit together. Novel stacked package designs called package on package (PoP) will be discussed with application for differential, high-performance interfaces like DDRx, PCI Express, SATA. The paper will show how to incorporate critical layout effects from the IC, Package, and PCB to evaluate system performance. By harnessing the power of today’s compute power combined with clever data management, this paper shows how to solve very large packaging problems accurately and efficiently. The many advantages, including the ability to rapidly analyze various routing alternatives, will be shown throughout the work. Post route verification for the full design using 3D EM tools will be highlighted and statistics regarding set up and solve time will be shared. Finally, proper de-embedding techniques will be discussed and simulated vs. measured data will also be shown to verify this new method.|
|Wayne Nunn, Sr. Package Characterization Engineer
San Jose, CA