Here is the abstract you requested from the DPC_2007_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3D Integration – Advances in Chip-to-Wafer and Wafer-to-Wafer Manufacturing Schemes|
|Keywords: 3D Integration, wafer-level chip stacking, chip-to-wafer|
|The technical feasibility and the unique technical potential of 3D interconnects created by wafer bonding or chip-to-wafer bonding have been analyzed in detail during the last years and are widely acknowledged in the industry. Today the focus lies on innovative manufacturing and integration schemes, which meet both, the economic and technical demands. Layer transfer on wafer level using aligned wafer bonding has the advantages of higher throughput, enhanced cleanliness, and the flexibility that standard fab equipment can be used. 3D stacking using chip-to-wafer bonding focuses on the yield, the “good known die” issue. Dies of different size can be integrated, e.g. several small dies on one big base die, enabling unchallenged small form factors. Furthermore the dies can be produced on different substrate materials, on different wafer sizes, and in different fabs by different producers. This flexibility results in very short time-to-market. The modular concept allows integrating standard components, which significantly reduces the development costs. In this paper a higher emphasis lies on the key enabling manufacturing technologies and supported processes. a) Device stacking - wafer-to-wafer (W2W) and chip-to-wafer (C2W) State-of-the-art integration schemes and process solutions are reviewed. b) Compared to all other stacking and integration approaches chip stacking on wafer-level has the inherent advantage that further processing can be performed on fab equipment without any restriction. Therefore W2W is an ideal way for multi-stacks. C2W targets mainly 2-tier stacks as it has limited post-bond processing capabilities on wafer-level. c) Via-first vs. via-last process flows A fundamental distinction between the different integration schemes is whether the vias are processed before (“via-first”) or after (“via-last”) chip stacking. Via-first approaches require mounting of the device wafer on a handle wafer. A novel thin wafer handling concept based on temporary wafer bonding enables to process the back-thinned wafer on standard equipment. d) Through-wafer via applications for C2W require a metal-metal thermo-compression bond where the bond pads are used as connection for the vias. Via last approaches are not feasible as technologies like CMP cannot be applied. For W2W a broader range of bonding methods is available. Via-first and via-last have both been demonstrated and qualified for direct bonding, adhesive bonding and metal-metal wafer bonding. e) High density vs. low density interconnects Due to the limited silicon real estate for interconnects, a higher interconnect density requires smaller bond pads together with high precision alignment processes. On C2W pick-an-place tools high alignment accuracy comes at the cost of throughput. For economical reasons W2W approaches seem to be more suitable for high density interconnects.|
|Thorsten Matthias, Director of Technology, North America