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Back-End Copper Plating for 3D Chip Stacking Applications
Keywords: Copper, Plating, 3D chip stacking
Various copper plating processes can be used for 3D chip stacking applications; bumps (such as studs and pillars), redistribution lines (RDLs), and through-silicon-via (TSV) electrodes. We developed three kinds of copper plating processes and compared technical differences. Bump plating : The chemistry and process are designed for high rate deposition due to the thickness of deposits (up to 110um) and the simplicity of die pattern. Mass transport of metal ions through the thick resist is a key factor affecting maximum deposition rate. With an optimized condition, we achieved the deposition rate of 2-4um/min depending upon open area and resist thickness. RDL plating : We modified our bath compositions and process conditions from bump plating conditions in order to get better within-die thickness uniformity, because die patterns are much more complicated and the deposit thickness is much thinner (typically, < 7um). Therefore, the plating bath and process are designed for high throwing power rather than high speed. We selected the deposition rate of 0.5-2um/min with a modified bath and process condition. TSV electrode plating : We investigated the impact of various deposition conditions on the overall filling capability within high aspect ratio vias and found that reducing current crowding at the via mouth and mass transfer limitations at the via bottom is critical in achieving void-free filling. This condition can be achieved only with a proper combination of seed conformality, surface wettability, bath composition, waveform, current density, and flow conditions. With an optimized condition, we achieved super-conformal, void-free filling with various via dimensions.
Bioh Kim, Business Development Manager
Semitool, Inc.
Kalispell, MT

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