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An Electronic Packaging Roadmap
Keywords: Packaging Design, System Level Integration, Nanomaterials
The demand for high-performance, lightweight, portable computing power is driving the industry toward miniaturization at a rate not seen before. Electronic packaging is evolving to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. Traditionally, greater wiring densities are achieved by reducing the dimensions of vias, lines, and spaces, increasing the number of wiring layers, and utilizing blind and buried vias. However, each of these approaches possesses inherent limitations, for example those related to drilling and plating of high aspect ratio vias, reduced conductance of narrow circuit lines, and increased cost of fabrication related to additional wiring layers. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. Assembly and packaging are bridging the gap by enabling economic use of the third dimension (3D packaging). System level integration is emerging. These approaches include System-in-Package (SiP), stacked die, or package stacking solutions. In addition to the trend toward miniaturization, new materials and structures are required to keep pace with more demanding packaging performance requirements. High speed packages, for example, as required for server and telecom applications, require low loss materials, better shielding, elimination of via stubs, and optical interconnection, both chip-to-chip and between packaging components This paper discusses a number of novel methods for extending packaging performance beyond the limits imposed by traditional approaches. One strategy allows for metal-to-metal z-axis electrical interconnection of subcomposites during lamination to form a composite structure. Conductive joints are formed during lamination using an electrically conductive paste. As a result, one is able to fabricate structures with vertically-terminated vias of arbitrary depth. Replacement of conventional plated through holes with vertically-terminated vias opens up additional wiring channels on layers above and below the terminated vias, and eliminates via stubs which cause reflective signal loss. Vertically terminated vias facilitate a more space-efficient package redesign. In addition, parallel lamination of testable subcomposites offers yield improvement, shorter cycle times, and ease of incorporating features conducive to high speed data rates. A proposed extension of this z-interconnect technology that provides for stacked memory packages will be discussed. A key element of this package is incorporation of integrated decoupling capacitance layers. This structure provides for very compact SIP / SOP devices where the semiconductor die can be tested and burned-in (Known Good Die) prior to final package assembly. Thinned die, embedded capacitance and z-interconnect of the die stacks provide for the ultimate compact package. Use of nanomaterials to enhance the conductivity of electrically conductive pastes, form printable integrated resistors with controlled sheet resistance, and form capacitors with high capacitance density will be presented. Development of roll-to-roll processes for high-volume manufacturing of high-performance packaging will also be addressed.
Voya R. Markovich, Senior Vice President and Chief Technology Officer
Endicott Interconnect Technologies, Inc.
Endicott, NY
USA


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