Here is the abstract you requested from the DPC_2007_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Fabrication of 3D Packaging TSV using DRIE|
|Keywords: 3D Packaging, DRIE, Through Silicon Via|
|Emerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch through-silicon via (TSV) for advanced interconnections. The interconnection step can be done prior to or post CMOS manufacturing, each requiring different etch process performances. A review of the DRIE capability in terms of etching profile, etch rate, etch depth has been carried out. Excellent tool flexibility allows a wide range of basic and complex profiles to be achieved. Unlike other techniques, DRIE has the capability to etch feature sizes ranging from sub-micron to millimeter width. The main specificity of the DRIE is that etch rate is sensitive to the total exposed area and the aspect ratio. For the TSV applications, where the total exposed area is lower than 10%, high etch rates are achievable. A study has also been done to highlight the importance of via profile for the success of the refilling step. In addition, due to the high flexibility of DRIE, we also explore the capability of using this technique for wafer thinning and plasma die separation.|
|Jean-Marc Thevenoud, Product Manager
Alcatel Micro Machining Systems
Annecy, Rhône Alpes 74000,