Here is the abstract you requested from the DPC_2007_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Assembly Strategies for 3D-Integration; Wafer-to-Wafer versus Chip-to-Wafer|
|Keywords: 3D, Stacking, Chip-to-Wafer|
|With the advent of 3D Integration concepts and wafer stacking as a potential enabler for the continuation of Moore’s law, the aligned wafer bonding requirements have shifted significantly. The post bond alignment accuracy requirements have increased by approximately an order of magnitude into the range of 0.5um-2.5um. Post-bond alignment precision across the wafer represents the gating element defining size and density of layer-to-layer interconnections. Chip-to-Wafer bonding and wafer reconstruction represent alternative or complementary solutions to improve yield and chip size flexibility. The following paper reviews the pros and cons of the two methods and the impact of the density increase on the assembly equipment.|
|Gilbert Lecarpentier, International Product Manager