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3D SiP Developments and Trends
Keywords: 3D SiP, Trends, POP
Invited talk per James Lu: Wireless and mobile phone products have driven the need for more functionality in the same or smaller handheld device. As a result the stacking of functional devices in the vertical dimension within the semiconductor package has come to fore. The prevailing method for integrating devices in the vertical dimension is die stacking. This works well for memory stacking, but the types of devices and systems that need to be integrated into a package has become more complex. To accomplish such 3D integration, the question arises what is the most effecient method: System on Package (SiP) or System on Chip (SoC). Each has inherent advantages and disadvantages. This paper will explore the trade-offs between 3D SiP and 3D SoC and recent developments and trends with respect to 3D SiP will be reviewed.
Flynn Carson, Director, 3D Packages
STATS ChipPAC, Incorporated
Fremont, CA

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic