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Wafer Level 3D Integration: 2007 Status Report
Keywords: 3D, Integration, Wafer Level
An emerging device architecture, and corresponding technology, referred to as 3-D IC integration is based on the system performance gains that can be achieved by stacking chips and vertically interconnecting, using through silicon vias (1-4) Replacing long 2-D interconnects with shorter vertical (3-D) interconnects has the potential to alleviate the well-known interconnect (RC) delay issues.
Dr. Philip Garrou , Consultant
TechSearch International, Inc.
RTP, NC
USA


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