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C4NP Reliability and Yield Data for Lead Free Wafer Bumping
Keywords: Bumping, Flipchip, Lead Free
Semiconductor packaging continues to migrate from wire bond to flip chip first level interconnect to meet size, weight and electrical performance requirements. Solder electroplating is commonly employed for wafer bumping, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, from FCiP to CSP bump dimensions. As the industry migrates to 300mm wafer processing and lead-free flip chip interconnect, C4NP is establishing itself as a viable solder bumping alternative. This paper reviews the latest lead-free reliability data for both, plated and sputtered UBM structures based on IBMs standard test vehicles. The test vehicle wafers were processed through plated or sputtered UBM formation and solder was applied using the C4NP process. After dicing, chips were assembled to organic chip carriers. These packages were then subjected to standard JEDEC preconditioning, assembled to cards or inserted in sockets, and subjected to a set of standard reliability stresses. These tests included: temperature/humidity/bias, high temperature storage, thermal cycling, low temperature storage, tin whisker testing, and electromigration. Yield information from 300mm wafers processed with C4NP is reviewed. This includes metrology data (solder volumes, heights and diameters), as well as defect levels and defect types per wafer. C4NP is a novel solder bumping technology developed by IBM which addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for bumping with a variety of high performance lead free alloys. The data in this paper is provided by the IBM Systems and Technology Group in the Hudson Valley Research Park, NY.
Eric Laine, Technology Specialist
SUSS MicroTec, Inc.
Chenango Bridge, NY
USA


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