Here is the abstract you requested from the DPC_2007_FlipChip technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Embedded Capacitor Technology for High Performance Microprocessor Packages|
|Keywords: Embedded Capacitors descrete and Planar, Microprocessor Packaging, Power Distribution, Signal Integrity|
|The integration of embedded Thick Film capacitors and polyimide based planar capacitor materials in IC packages has been investigated in a joint program sponsored by DuPont with the Georgia Institute of Technology Packaging Research Center (PRC). The PRC provided fabrication, electrical modeling and simulation capabilities and DuPont provided the component materials. Test vehicles with different designs were designed, fabricated and tested. The test vehicles included embedded ceramic-fired-on-foil capacitors with microvia interconnects and structures with planar capacitor layers. Measured electrical performance data were used to create models of alternative package designs and to perform simulations to determine the designs offering the most effective power delivery and noise decoupling for a high performance semiconductor package. To demonstrate the performance of embedded Thick Film fired-on-foil capacitors, test vehicles with different capacitor configurations were designed, fabricated and tested for individual capacitor characterization. The test vehicles included capacitors with microvia interconnects and two sequential build-up layers on each side of a bismaleimide triazine (BT) core. Feature sizes were 12 micron lines and spaces and 50 micron diameter microvias. Other test vehicles used a core layer without build-up layers, planar capacitor layers and arrays of individual embedded capacitors with different size, type and interconnection designs. Each capacitor variation was electrically characterized to select the preferred capacitor design having the best combination of electrical properties and frequency performance. The electrical performance data from the test vehicles was used to create models of alternative package designs and to perform simulations to determine the designs offering the most effective power delivery and noise decoupling. A companion program was initiated with the PRC to demonstrate the performance of thin dielectric Planar capacitor power plane layer test vehicles were developed and tested. Reduction of simultaneous switching noise in high speed buses was demonstrated on these active (IC-driven) and passive test vehicles containing 50 ohm single-ended and 100 ohm differential transmission lines.Based on measured results, simulations of typical microprocessor serial bus configurations were performed showing that thin (1 mil) planar power distribution layers are very effective in reducing simultaneous switching noise, jitter and signal attenuation, especially on single-ended termination, high speed transmission lines. This paper will describe the test programs and results demonstrating the advantages of low inductance Thick Film embedded capacitor technology and thin planer power distribution layers typical of microprocessor packaging applications.|
|Daniel Amey, Research Fellow
E. I. DuPont Electronic Technologies
Research Triangle Park, NC