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Optimize Flip Chip Interconnect Design using Designed Experiment Approach with 3D Modeling and Simulations
Keywords: Flip Chip, Interconnect, Design
Low-k interlayer dielectrics (ILD) have been in volume production for several years. However, the package impact on the mechanical integrity of the low-k interconnect structures in the die has been proven to be significant. A low defect level of ILD delamination beneath the flip chip component bond pad has been reported by several manufacturers. Although steps can be taken to eliminate this in current low-k designs, the occurrence rate of this defect can increase as ultralow-k (ULK) materials and lead-free solder interconnects are introduced for future technology nodes. This paper will reflect on the importance to refine interconnect design to minimize stress in the ILD during the flip chip packaging assembly process. There is an endless number of low-k dielectric and package configurations possible with limited time and resources available to understand the impact of each variable; therefore, the approach to understanding the overall impact requires modeling and selective experiments to confirm the model predictions. This paper introduces a designed experiment approach to evaluate the impact of more than ten interconnect design variables on ILD stress during the flip chip die attach reflow process. Stress is calculated using a 3D model and simulations. Variables considered in this paper include last metal copper bond pad design, redistributed metal design, polyimide design, die thickness, package thickness, and die size among others. The response variables are various calculated stresses generated using a 3D flip chip package model and mechanical simulation.
Brett Wilkerson, Flip Chip Integration Engineer
Freescale Semiconductor
Austin, TX
USA


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