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Defect Free Through Silicone Via Fill with Minimum Overburden
Keywords: 3D, Silicone , MEMS
President and CEO of Samsung Electronics, Dr. Chang-Gyu Hwang stated on December 12, 2006 that we are entering a technology fusion era that promises to offer tremendous global opportunities for expanded use of 3D silicone-based technology. The heart of 3D silicone-based technology is Cu filled vias which allow direct die-to-die, die-to-wafer, and wafer-to-wafer connections. The technology of choice today to make these Cu vias is by electroplating. Though electroplating Cu for interconnect is a well known technology owing to its wide use in Cu damascene, it proves to be quite a different ball game for through silicone via fill when via diameter changes from nm to tens of microns; via depth changes from sub microns to hundreds of microns. What we have learned about Cu damascene and what works could not be applied without modification to through silicone via fill. In this paper, we will describe main hurdles to achieve a perfect, defect-free fill, and what we could do to overcome these problems. We will also discuss how to reduce the overburden on wafer surface.
Dr. Yun Zhang, Director, Research and Development
Cookson Electronics - Enthone Inc.
Jersey City, NJ
USA


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