Device Packaging 2019

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Ultra Low Temperature Testing of an Ultra Low Power CMOS Synchronously Clocked Complex Logic Circuit
Keywords: ultra low temperature, ultra low power, leakage current
This paper reports on the ultra low temperature (ULT) testing and verification of the CMOS Ultra Low Power Radiation Tolerant (CULPRiT) integrated circuit technology developed at CAMBR for NASA aerospace applications. This 0.5 volt logic fabricated at AMI has been proposed for operation in the cold environs of deep space, particularly in applications where low power consumption is needed. For example, CULPRiT has been suggested for use in a deep canyon Mars mission where solar energy is limited and temperatures are extremely low. We performed the first cryogenic test of a complex synchronous logic ultra low power (ULP) system (~1000 flip-flops) to below 20 degrees Kelvin. This NASA standard communication processor is the same device flown successfully on the ST-5 mission in the spring of 2006. Included in this test was a discrete ULP MOSFET transistor on another test chip. The results were encouraging and demonstrated both the ULT performance improvement and the shift of electrical operating parameters (i.e. bias conditions) of CMOS electronics operating at low temperatures. At ULT we observed threshold voltage and transconductance increases. From a ULP standpoint in particular, a significant order of magnitude reduction in the sub-threshold leakage current occurred. This gave our clocked logic a greater than fifty percent reduction in power consumption at ULT versus room temperature (RT). Due to a support electronics limitation at ULT we were unable to verify a theoretically suggested increase in maximum operating frequency. Further study is indicated and the parametric observations suggest that a CULPRiT design optimized for ULT operation will be a viable component for future space exploration. Index Terms-Cryogenic cooling, threshold voltage (VT), transconductance, ultra low power (ULP), ultra low temperature (ULT).
Ronald O. Nelson, Research Engineer
University of Idaho; Center for Advanced Microelectronics and Biomolecular Research (CAMBR - UI)
Post Falls, ID

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