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2nd and 3rd Level Solder Joint Reliability of High-End Flip Chip SiP (System in Package)
Keywords: System in Package(SiP), Flip chip, Solder joint reliability
Major concerns of flip chip type SiP (System in Package) for network application are 2nd level interconnection for memory package solder joint on SiP substrate and 3rd level for SiP solder joint on system board, which were critically induced by thermo-mechanical stress and SiP construction on 55x55sqmm large package body size. In this paper, 2803pin flip chip SiP was evaluated for SiP construction and material set optimization by using FEA (Finite Element Analysis) and DOE case studies. 3 different heat spreader construction, heat spreader thickness, and underfill implementation were considered in stress and fatigue lifetime FEA case studies and lone-term solder joint reliability, ATC (0~100degC) test. Another important factor in system level reliability was an external heat sink and its compressive force effect was also investigated in ATC test. In addition, short-term mechanical reliability test was also evaluated for 2803pin FC SiP qualification, 4 point monotonic bend test based on IPC-9702 spec and mechanical vibration test based on JEDEC standard were carried out for 2nd and 3rd level solder joint reliability. Finally actual experiments result was compared with FEA data in correlation process.
Sang Ha Kim, Staff Packaging Engineer
NEC Electronics America
Santa Clara, CA

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