Here is the abstract you requested from the IMAPS_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Silicon Technology Development and the Impact on ESD Design with Advanced IC Packages|
|Keywords: ESD, Silicon Technology, IC Package Effects|
|It is well known now that rapid advances in silicon process technologies into the nanometer regime are essential to enhance IC performance and at the same time newer circuit development techniques need to be state-of-the-art to achieve the required high speed circuits in the GHz range. These effects, when combined together, are already limiting the ability to meet the ESD protection design requirements. The third dimension to this negative impact for ESD design can critically come from the large package size effects, especially for the so called Charged Device Model (CDM) stress. Other features such as stacked die packaging are introducing further complexity to ESD design and testing. However, in some cases the package development has had some beneficial effect in making the vulnerability to the Human Body Model (HBM) much less. All of these new issues point to using a more realistic view of ESD in the production control areas and specifying revised and safe ESD specification targets that are commensurate with the nanometer technologies. This paper will first review the technology and circuit trends that are making ESD design a difficult task, followed by identification of the specific package development issues that further restrict the ESD design. The paper will focus on the following issues: 1) IC package historic roadmap and the general impact on ESD, 2) package size and its impact on CDM protection design, 3) package changes and their differences of vulnerability to HBM effects during handling, and 4) most recent package advances and the expected impact on both HBM and CDM. All of these issues will be tied together in discussing an ESD roadmap that comprehends realistic ESD specification goals for the near future. The paper will also pose challenges to the package development community in important technical developments needed for future ESD design.|
|Charvaka Duvvury, Texas Instruments Fellow