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Determining the Effects of Package Parasitics on SI and EMC Performance
Keywords: package, parasitics, noise
Signal Integrity and EMC problems are significantly affected by package parasitics. Such effects can be especially problematical for cases where devices undergo a die shrink in the same package. This paper will describe a simple method of determining the effects of package parasitics for a broad class of chip packages. The paper will start by reviewing conclusions of a previously published paper by this author on a basic method, adding significant new data, and extending the method to both signal integrity and EMC problems as well as how to spot each kind of problem. Examples of problems that have occurred and how to avoid them will be presented. New insight will also be provided on die to heat sink coupling of high frequency signals. The basic method involves measuring inductive voltage drops across package structures, such as bonding wires, using an easy to construct square loop, a fast scope, scope triggering settings, and mutual inductance. The real value comes in interpreting the scope plots. This paper will relate scope plots to potential problems complete with "war" stories. Even if significant noise is identified, it may not actually result in a problem. A method will be presented to determine when the observed noise will actually become a problem. Previous Paper Reference: A Method for Troubleshooting Noise Internal to an IC, Douglas C. Smith, Proceedings of the 1997 IEEE EMC Symposium, pp. 223-225, http://emcesd.com/pdf/emc97.pdf
Douglas C. Smith, Consultant
D. C. Smith Consultants
Los Gatos, CA
USA


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