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Assembly Technology for 3-D VLSI Chip Stacks
Keywords: chip stacking, 3D packaging, 3D assembly
Though a great deal of work is going into wafer stacking for 3-D VLSI ICs using through silicon via (TSV) processing, wafer assembly may not be the best way to build 3-D systems from VLSI elements. Systems need more than silicon. In the case of our 3-D RF program, we need to assemble both GaAs and silicon layers with TSVs, remove significant amounts of heat, provide integrated decoupling and power distribution, and avoid cumulative yield issues by pretesting individual die layers before assembly. As each layer is a miniature subsystem, Z-axis interconnect demand can be satisfied by connections on 100 - 200 micron pitch. This paper describes our concept for an integrated assembly and cooling method for 3-D VLSI systems. To deal with the CTE mismatch of different materials, plated compliant copper posts are used to make connections between layers. The copper is also used to form a fluid dam around the resulting channel between each pair of die. Circulating fluid is pumped through these channels for heat removal. Sequential attachment of pretested layers is accomplished by forming copper/tin intermetallic compounds. We have developed a system for plating 100 micron high, 30 micron diameter copper posts using KMPR photoresist. At the same time, we plate the fluid confinement dam that will be joined to the successive chip. These structures are topped with plated tin, and can be mated to a corresponding set of copper pads on another silicon layer using a flip chip bonder. This paper reports on the process development and assembly of daisy chain test vehicles designed to examine assembly yield for the attachment process. Progress on an integrated test vehicle with several fluid-cooled layers will also be reported. This novel concept for packaging miniature 3-D VLSI systems appears well-suited to high power RF applications.
Leonard Schaper, Professor
University of Arkansas
Fayetteville, AR

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