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|Large Die Fine Pitch Flip-Chip Bumping Technologies for Cu/Low-k Devices Applied High Density Flip-Chip Ball Grid Array (FCBGA) Packages|
|Keywords: Flip-chip bumping, Cu/low-k, Flip-chip BGA|
|The interconnection structures have changed from Al/SiO2 to Cu/low-k according to requirement for high performance of electronic parts and flip-chip bumping technologies required by size reduction and high performance as well as cost effectiveness compared with conventional packaging. However, low-k dielectric structure are mechanically weaker compared to previous dielectric materials and in case of applied high density Pb-free bumping, stress level in low-k layer underneath the bumps more increased because of tighter bump pitch and higher process temperature. In this study, flip-chip bumping technologies for Cu/low-k devices with large die fine pitch have been studied in terms of process, structure and reliability. Regarding the bumping, all processes and structures were designed to reduce the stress level in Cu/low-k layer underneath the outermost bump. Cu/low-k devices used in this study had 3 Cu/low-k stacks, 20 x 20 §± die size and about 3200 I/Os. Before bumping on Cu/low-k devices, the test die with bump layer was fabricated on 25 x 25 §± Si bare wafer and 17.5 x 17.5 §± low-k stacked wafer and the stability of bump structure and processes were verified by shear fracture test after 10times multi-reflow with Pb-free condition and TC. To optimize the bump structures for Cu/low-k device, 3 types bump structure with redistribution and passivation layer were designed. Redistribution and bump layers were formed by electroplating method. For the Cu/low-k devices with each bump structure, shear fracture test was performed after 10 times multi-reflow with Pb-free condition and confirmed the off-pad structure without failure. After that, the dimension of each layer such as via size and dielectric thickness were tuned to reduce the stress in Cu/low-k stack layer underneath bumps. To confirm the reliability of optimized bump structure, Cu/low-k devices with optimized bump structure were applied the high density FCBGA PKG and performed the reliability tests of the MSL3 and TC (-40¡É/125¡É) in PKG level.|
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