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Investigation of Advanced Via Plating Process for Via Interconnection Enhancement
Keywords: package substrate, via plate, reliability
Recently, requirement for packaging substrate is greatly increasing in the electronics industry. As packaging substrate is directly interconnected with chip, packaging substrate is required to technologies of high density and high speed trends. For correspondence of high density and high speed trend, there are several challenges such as fine circuit pattern, fine micro via, high electric characteristics, high reliability and multi-functions. To realize such challenges and to develop packaging substrate of high density and high speed, the advanced process and the reliability enhancement should be demanded. It is very important to enhance via interconnection for reliability improvement in packaging substrate, because via interconnection is directly concerned with reliability of packaging substrate. And the incorrect via interconnection is very often happened in packaging substrate manufacturing process. As via hole size makes smaller, electroless copper is insufficiently plated in via hole inside. Because of this insufficient plating in smaller via hole, it should be happed to the incorrect via interconnection and reliability problem. In this study, the advanced via plating process was investigated and analyzed to solve reliability problem in via interconnection. Via plating experiment was variously executed for improvement of via interconnection. Based on the experiment result, it could be confirmed that via interconnection properties was enhanced in the via hole manufactured with advanced plating process.
Jung-Hwan Park, Engineer
Samsung Electro-Mechanics Co., Ltd.
Suwon, Gyunggi-Do 443-743,

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