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Challenges Associated with Lead Free Bump Qualification for the 65 nm Node
Keywords: Pb-free bumps, Flip-Chip on SLC and HITCE substrates, 65 nm node qualification
90 nm was the first challenging flip-chip bump qualification, being the very first one technology node to utilize Low-k dielectric. The 65 nm would have been a small step forward from a qualification point of view, but for environmental issues and the ROHS laws in Europe and Asia, customers are looking for a total lead-free solution, which does add a new twist to the qualification. Another subtle advantage for the lead-free bumps is they offer better electromigration performance as compared to eutectic bumps. For this project, Avago Technologies ASIC Products Division (APD) partnered with Amkor Technology to come up with a systematic way of developing an assembly process that can be qualified with minimal problems for the SLC laminate and HITCE ceramic substrate technologies. This paper will discuss the development and qualification methodology utilized to bring this process up and ready for production in the shortest possible time and the budget constraints. Details will also be provided for the test vehicles used for this evaluation, the Design of Experiments conducted and generic material information for underfills, fluxes etc. The component level reliability test data will be provided and discussed, which will include temperature cycle, high temperature storage and biased HAST tests. Manufacturing process robustness will be demonstrated by extending the life cycle test to 2000 cycles of temperature cycle and 2000 hrs of high temperature storage. Finally, the frozen process parameters will be detailed and discussed.
Uday Vissa, Packaging Technology Engineer
Avago Technologies
Fort Collins, CO
USA


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