Here is the abstract you requested from the IMAPS_2007d technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Reliability of BGA and MicroContact Packages Under Shock Loading|
|Keywords: MicroContact interconnect, Drop testing , JSED-B111|
|Portable consumer electronics is a rapidly growing market segment for modern electronics devices which includes lightweight systems such as cell phones, laptop computers, PDAs, etc. Due to ever increasing demand for integration of higher functionality, miniaturization is a parallel ongoing trend for design of microelectronics packages used in such devices. One of the main challenges involved in keeping up with this trend is maintaining reliability of second level interconnects for these packages with respect to mechanical/thermomechanical loading. Board level drop or impact response of a package assembly is an increasingly important facet of the reliability evaluation. Rupture of second level interconnects (solder joints) and test board pads/trace failures are the most commonly observed modes of failure due to shock loading conditions. Various design and test parameters such as materials, geometry and loading configuration affect the failure mechanism involved. This paper describes numerical (Explicit Dynamic Finite Element Analysis) and experimental approach to compare two interconnect designs – a new design called MicroContact and a most commonly used BGA (Ball Grid Array) for their response to shock loading conditions. The MicroContact design is intended for higher adaptability to increasing I/O density and improvised test/burn-in capabilities. Experiments are performed according to JEDEC board level shock testing standard JESD22-B111. Detailed numerical models are analyzed and geometric parameters such as interconnect pitch and solder volume are varied to evaluate transient structural response of the interconnect designs.|
|Piyush Savalia, Reliability Engineeer
San Jose, CA