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Multi-Decade Gigabit SiP with over 20 Metal Layer PALAP FCBGA Substrate
Keywords: PALAP (PAtterned prepreg LAy up Process), SiP (System in Package), Virtual SiP
System in Package (SiP) is a promising solution, providing cutting-edge device technology to the market years ahead of the System on Chip (SoC) solution. The SiP substrate has to provide ultra-high speed die to die data links in order to integrate high-end and high-speed communication devices built into a single package. This paper discusses the design challenges for a multi-decade gigabit (~40Gbs) SiP based on the PALAP (PAtterned prepreg LAy up Process) FCBGA technology. One of the most important design stages of the SiP is the feasibility study which dominates the overall system performance. The critical design issue at this stage, especially for ultra-high speed systems, is how to meet the signal/power integrity requirements. A virtual SiP design methodology has been developed which is capable of conducting feasibility studies in order to meet these requirements. This design methodology is capable of performing signal/power integrity simulations on multi-decade gigabit systems. The virtual SiP design environment consists of a pseudo-vertical wave guide, multiple-graded speed signal lines and a loss-less resonance-free power delivery design scheme based on the PALAP FCBGA technology. These components are combined with simplified die model components including signal source, switching noise source and die passive elements. The high frequency modeling technology derived from PALAP FCBGA has been further enhanced to support complex and larger modeling sizes of the SiP substrate. An experimental SiP substrate has been designed by implementing this virtual SiP design environment and has been fabricated and evaluated. The result showed, in measurement, 40GHz 3dB bandwidth for the longest signal line (~30mm) even with a single-ended signal. The signal wave simulation, done by using measured S-parameters, showed a successful small jitter 40Gbps signal transmission with single-ended signals, which suggests that designers can use normal small signal transceivers for die to die data link without using the high-cost and high power consuming SerDes technology. The measured electrical characteristics have been well correlated with the electrical models up to ~40GHz.
Ryuichi Oikawa,
NEC Electronics Corporation
Kawasaki, Kanagawa 211-8668,
Japan


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