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The Effect of Dielectric Polymer Layer Thickness on WLCSP Reliability with Variation of Elastic Modulus
Keywords: WLCSP, thermal fatigue, solder joint reliability
Hynix Semiconductor has developed WLCSP without underfill, called Omega-CSP for high speed DRAM application. This package consists of the 1st dielectric polymer layer as an insulation layer, Ti/NiV/Cu sputtered seed layer, Cu electro-plated redistribution patterned layer, the 2nd dielectric polymer layer as solder resist, and solder ball. The 1st dielectric polymer layer of Omega-CSP has a high CTE and high elastic modulus to increase the total WLCSP CTE resulting in the relaxation of the thermal strain generated at the solder joint. In this study, board level thermal fatigue property of WLCSP was investigated in relation to the 1st dielectric layer modulus, 1st dielectric layer thickness and chip thickness by using Omega-CSP. The purpose of this research is to investigate the effect of the 1st dielectric polymer modulus and thickness on board level thermal fatigue life. Generally, the increase of the 1st dielectric polymer layer thickness improves the board level thermal fatigue property because the thick polymer layer absorbs much more stress induced by CTE mismatch between chip and board. However, in this study, the WLCSP sample with thin polymer layer has showed better thermal fatigue property than thick polymer layer. This result appeared to be related with elastic modulus of the 1st dielectric polymer layer. The use of high modulus dielectric polymer causes package warpage additionally by CTE mismatch between chip and dielectric layer during thermal fatigue test. This warpage generate an additional stresses at solder joint and weaken the thermal fatigue property. So the thick polymer layer with high elastic modulus appears to deteriorate the board level thermal fatigue property. From the result, it was concluded that the thicknesses of dielectric polymer layer should be designed properly when the high modulus dielectric polymer is used as an insulation layer.
Jong Hoon Kim,
Hynix Semiconductor Inc.
Icheon-si, Kyoungki-do 467-701 ,
S. Korea


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