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Wafer-Level System Integration Technology Based on Device Redistribution Process for MEMS on Chip
Keywords: Wafer-Level System Integration, Device Redistribution, RF-IC
High-density and high-speed electronics packaging technology is progressing rapidly and has become indispensable for realizing high-performance electronics products such as personal mobile phones. Currently, MEMS integration technologies, which enables to integrate MEMS and LSI devices as MEMS on chip, are highly required to enhance system performance, raising it to a level surpassing that achievable by the individual MEMS and LSI devices in SIP. The authors have developed a wafer-level system integration technology for MEMS on chip by applying the device redistribution process, which incorporates heterogeneous KGD, and inter-chip layer process for ultra-thin RF receiver chip. The wafer-level system integration process consists of three main steps: KGD device redistribution process to implement system integration for realizing MEMS integration, inter-chip layer formation for realizing interconnection between KGD devices, and wafer grinding process for achieving ultra-thin RF receiver chip. The RF receiver chip, whose size is 6.0mm ~ 6.0mm ~ 0.7mm, was prototyped to confirm the package density compared with the conventional SOC or SIP. The RF receiver chip has a KGD RF-IC device and passive components in epoxy resin and polyimide insulation layer. The RF-IC and passive components have interconnection with inter-chip layer. From the results of the prototype experiments, it was found that high precision of distribution for the RF-IC device and the passive components was achieved by the device redistribution process utilized precise device transfer method. Also, good results for the filling of the resin into the inter-chip gap between the RF-IC chip and several passive components were realized by vacuum printing method. Furthermore, the inter-chip layer showed excellent planarization on the RF-IC device and several passive components. Consequently, it was confirmed that the wafer-level system integration technology realizes integration 16 times higher than that attainable with conventional SIP technology.
Yutaka Onozuka, Research Scientist
Toshiba Corporation
Kawasaki, Kanagawa 212-8582,
Japan


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