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Abstract Preview
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| Thermal Management in 8-Strata 4 Gb DRAM SiP |
| Keywords: Thermal management, SMAFTI-type package, Stacked DRAM SiP |
| Many simulation analyses of thermal management have reported in recent years, but few examinations of 3-dimentional packaging structures have been conducted. This paper describes thermal management in an 8-strata 4Gb stacked DRAM SiP (System-in-aPackage) having TSV (Through-Silicon Via) structures, using a novel SMAFTI package. Since DRAMs are highly temperature-sensitive devices, the maximum junction temperature (typically 85deg-C) strictly limits the required thermal resistance.
First, we used 15mm square test structures to investigate the extent to which SMAFTI-type packages can contain generated heat. A SMAFTI-type package is a molded BGA package that contains a high-capacity memory and a logic die stacked across the feedthrough interposer in a chip-on-chip configuration. Through 3-dimensional thermo-fluid simulation, we obtained the junction-to-ambient thermal resistances (theta-ja) as follows: 30deg-C/W (no wind) and 21deg-C/W (wind: 3m/s). Further, a heat spreader attached atop the package decreased theta-ja by around 20%.
To validate these numerical results, we measured the thermal resistance of the assembled TEG packages with a JEDEC standard wind tunnel. The measured theta-ja for DRAM die were 26.9 (no wind) and 21.0deg-C/W (wind: 3m/s), which agree well with the simulation values. Considering the test structuresf small dimensions, these data indicate the high heat radiation ability of SMAFTI-type packages.
Next, we simulated a 33mm square prototype package of 8-strata DRAM SiPs. Theta-ja was 8.9deg-C/W (wind: 2m/s) when a heat spreader was attached. Thermal resistance decreased dramatically with the help of high thermal conductivity in high-density vertical interconnections such as TSVs and metal bumps.
Finally, we measured thermal resistance of assembled prototype packages containing 8-strata DRAMs and a high-speed logic die. From simulation and measurement, we confirmed that the DRAM temperature inside the prototype package can be kept lower than 85deg-C under the operational condition of 5W heat consumption in room-temperature air. |
Satoshi Matsui,
NEC Electronics Corporation
Kanagawa prefecture 229-1198,
Japan |
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