Here is the abstract you requested from the IMAPS_2007b technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Manufacture and Characterization of a Novel Flip-Chip Package Z-Interconnect Stackup with RF Structures|
|Keywords: RF Mixed signal, LCP, PTFE, APPE materials, Chip package|
|More and more chip packages need multi-GHz RF structures to meet their performance targets. The ideal chip package needs to combine RF features with Digital features for these applications. They drive low-loss, controlled-impedance transmission lines, flexibility in assigned signal and power layers, and clearances of various shapes in power layers. Building these features in a chip package is difficult without making the stack-up very thick and without compromising the reliability of the product. New stack-ups are developed using LCP material, PTFE and APPE material in combination with embedded passive materials which achieve the main features that an RF flip-chip package needs: Low-loss signal path Small, medium, large width, controlled-impedance lines Embedded passive components, discrete resistors and capacitors, plus capacitance layers Delay matching Islands in all layers, plane layers can be either power or ground Narrow lines for digital and low-frequency signals Arbitrary stack-up, symmetric or not, all layers have ground and signal regions Large, arbitrary-shaped clearances in planes Lightweight, thin This effort is an integrated approach on three fronts: materials development and characterization; fabrication; and design and electrical characterization at package level. The manufacturing and process flow to build these stack-ups will be shown. Typical design structures to utilize these stack-ups will be detailed. Electrical performance results will be displayed, including predicted values, simulation and data measured in lab. The electrical performance will focus on impedance and S-parameter results. Polymer nano-composites were used to fabricate thin film embedded passives. Nano-composites can be deposited either by thin coating or screen printing or by photo process. Capacitance values are defined by the feature size, thickness and dielectric constant of the polymer-ceramic compositions. Printable discrete resistors with sheet resistances ranging from 1ohm to 120 megaohm have been fabricated. Reliability of the composites was ascertained by IR-reflow, thermal cycling, PCT (Pressure cooker test) and solder shock. Electrical performance of the embedded passives will be analyzed and measured.|
|Michael Rowlands, RF Signal Integrity Engineer