Abstract Preview

Here is the abstract you requested from the IMAPS_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

The Effect of Package Pin Map on Signal Integrity for Test Applications
Keywords: package design, signal integrity, test socket
The continuously increasing operation speed of the ICs in the past decade has made the packaging design more challenging than ever. In order to deliver the signal from chip to PCB with minimal distortions, the signal integrity analysis has become a critical step of packaging design work flow. Such analysis is typically done at the package level, but with todays higher speed ICs pushing for less and less design margins at all levels, more and more companies have also realized the necessity of bringing the PCB signal integrity analysis into the equation to ensure the whole system level success. Unfortunately, very little thought has been given to include the test socket into the consideration during package design stage. The signal integrity analysis for test socket has been always an afterthought. As the result, the customers often have to use those so-called high bandwidth sockets to test their high speed products. Such sockets are usually very expensive and less robust mechanically. It is also very common for such sockets to have low first pass yield and require frequent maintenance. Hence the cost of testing is greatly increased directly or indirectly by using such sockets. However, if the package design engineer is aware of the existence of the test socket somewhere down the road and make certain package design arrangement accordingly, the need of such high bandwidth sockets can be greatly decreased. Even with arrangement simple as signal/ground pin map, the signal integrity performance of the test socket and package as whole can be greatly improved. Through some simple case studies, this paper will demonstrate how much such considerations during package design stage can improve the testability later on. Hopefully, the paper can also serve as a call for awareness of such new work flow for package design.
Dr. Hongjun Yao, Signal Integrity Manager
Antares Advanced Test Technologies
Gilbert, AZ

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems