Here is the abstract you requested from the IMAPS_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Board Level Drop Reliability of Package-on-Package|
|Keywords: package-on-package, board level drop, reliability|
|Application of package-on-package (PoP), which has stacked structure of top memory package over bottom logic package, is rapidly expanding owing to its advantage of cost, flexibility, test, repair, and so on. Drop reliability of PoP is very important because demand of PoP stems from mobile products, and proper design and material guide is required. Drop performance of PoP, which had the most popular size of 14x14mm2, was investigated by the board level drop test under the 1500G peak acceleration and 0.5ms duration time. Three or four daisy chain nets were formed for each PoP on the test board and simultaneously monitored during the drop test. Failure locations and modes were analyzed by the dye penetration test and the examination of cross-section of solder joints. Failures were observed mostly between the bottom package and board interface, especially at the package corner location. Various solder compositions and surface finishes of substrate and board were tested. The combination of OSP finishes with Sn1.2Ag0.5Cu0.05Ni solder ball showed best result. To reduce total PoP height, test vehicles with smaller solder ball or land grid array design were tested. Drop performance was deteriorated for both cases, thus different approach is necessary to reduce size. Further reduction of size and enhancement of performance can be achieved by introducing flip chip technology to the bottom package. There was no significant difference in the drop performance between flip chip type and wire bonding type PoP. As conclusion, proper selection of material and identification of weakest link are crucial factors to improve drop performance of PoP.|
|Seok Won Lee, Senior Engineer
Samsung Electronics Co., IPT Team, SYS.LSI Division
YongIn-City, Gyeonggi-Do 446-711,