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A Theoretical Statistical Analysis of Fiber-Weave Impact on High Speed Differential Signaling
Keywords: fiber weave, high speed differential signaling, statistics
The fiber-weave effect, where the propagation delay of a differential pair is skewed due to individual trace’s alignment to the fiberglass weave of the PCB, has been reported at DesignCon and other conferences. It has been shown that the impact on eye opening at receiver for high speed differential bus is strongly dependent on routing length and signal rate. In this paper, we extend the study using a theoretical statistical approach to evaluate the fiber-weave impact under practical HVM (high volume manufacturing) conditions, where: • Weave types can vary • The alignment between trace and weave can be very different for each individual pair; • In actual designs, some segments of routing are diagonal and not parallel to board edges, and are therefore much less susceptible to fiber weave impact • Among the segments that are parallel to board edges, the skew of different segments may cancel or add to each other, helping or worsening the impact. This paper takes a statistical approach and analytically answers the basic question: if I build millions of boards, how many of them will see an eye reduction of 1ps, 2ps, 3ps, …, respectively? The potential advantage is that it provides designers guidance on when to take actions based on what kind of risk they can tolerate. The full paper will detail the analysis approach, but here is a quick preview. • Perform a full link SI analysis without fiber-weave effect. • Generate transmission line models to incorporate multiple levels of fiber weave effect, and substitute into original simulation. • Establish a prediction formula between eye opening impact and the skew due to fiber weave. • Perform a Monte-Carlo simulation to prove the prediction formula is valid • Use the prediction formula to calculate eye impact under HVM conditions (distribution of the skew is published at DesignCon) The process has been applied as an aid to evaluate the risk of future designs.
Xiaoning Ye, Sr. Hardware Engineer
Intel Corporation
Hillsboro, OR

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