Here is the abstract you requested from the IMAPS_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Mechanical Reliability of Cu/Low-k Multi-Layer Interconnects in Flip Chip Packages|
|Keywords: Flip chip package, Cu/low-k interconnect, reliability|
|Flip chip ball grid array (FCBGA) package is used for high-performance ULSI chips because of the requirement of high I/O density. During packaging assembly, significant stresses are generated due to the thermal expansion coefficient (CTE) mismatch between chip and package. This chip-package interaction (CPI) will induce large stress to drive interfacial crack formation, which raises serious reliability concern particularly for Cu/low k interconnects due to the weak mechanical properties of low k dielectrics. In this study, we investigated the reliability impact of CPI on Cu/low-k interconnects in a flip-chip package for high performance ULSI chips, focusing on the effects of the wiring dimensions and the dielectric properties. A 3D sub-modeling technique was used to analyze the CPI using 4 sub-levels to link the deformation from the package level to the interconnect level. A modified virtual crack closure (MVCC) method was applied to calculate ERR and fracture mode at critical interfaces. The analysis was performed on four metal-layer interconnects with wiring geometries specified by the design rule where the crack driving forces at several low-k interfaces were calculated. If the same low-k material is used for all layers, the M4 interfaces show 2.5 times higher ERR than the lower levels. However, when TEOS is used in the M4 level, the ERR at M3 interfaces becomes 35% higher than the M4 level. In addition, when OSG is used in the M3 level and TEOS is used in the M4 level, the ERR at M2 interfaces is the highest. This indicates that wiring dimensions and ILD properties are important in controlling CPI. At the presentation, the effects of interconnect design rules for 65nm technology and beyond and low-k properties on the mechanical reliability of Cu/low-k interconnect will be discussed.|
|Chihiro J. Uchibori, Research Staff Member
Fujitsu Labs. America, Inc.