Here is the abstract you requested from the IMAPS_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Optoelectronic Packaging for 16-Channel Optical Backplane Bus using Volume Hologram Optical Elements for High Performance Computing|
|Keywords: Optoelectronic , PVGA, FPGA|
|Optical backplane bus not only can fulfill the ever increasing bandwidth demands in high performance computing but also allows the sharing of transmission medium to reduce wiring congestions. A 3-slot optical backplane bus demonstrator using photopolymer volume gratings array (PVGA) on top surface of glass substrate to fan-out light beam is designed to allow 16 channels of data to be broadcast from central slot to two daughter slots or uploaded from any daughter slot to central slot. Alignment tolerance of the optical interconnect system is investigated theoretically and experimentally. By analyzing the diffractive characteristics, the 3dB bandwidth limit of the optical layer is determined to be more than 36nm. By carefully aligning the fabrication system, the incident angle deviation from Bragg condition is reduced to below 0.1„a, much less than the 0.7„a angular tolerance. The variation of the hologram efficiency is below 3dB by optimizing the recording beams. In the optical sub-system, VCSELs and photodetectors packaged in the form of TO-46 can are assembled on top of each PVG and interleaved to reduce the crosstalk to below noise level. Three computer mother boards using FPGA are made to verify the data transmission among the slots. Interface boards between the FPGA boards and optical transceivers are designed and fabricated to separate the implementation of digital layer and optical layer. Above 4.8Gbps aggregated data transmission is successfully demonstrated using the multi-channel system. Single channel transmissions at 10Gbps data rate is also tested with above 100uW input power, showing the potential to improve the total two-way bandwidth to above 102.4Gbps.|
|Prof. Ray Chen , Professor
University of Texas