Here is the abstract you requested from the Passives_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|The Use of Embedded Planar Capacitors for I/O Decoupling|
|Keywords: embedded planar capacitor laminates, noise and jitter reduction, high frequency decoupling|
|Current trends in the electronic industry for increasing miniaturization of electronic products has led to the integration of components within semiconductor packages and boards. Traditionally, discrete decoupling capacitors placed on the surface of the board or the package have been used to decouple active switching circuits. However, with increasing clock rates and their higher harmonics, decoupling has to be provided in the GHz range. Discrete decoupling capacitors are no longer effective in this region because of the increased inductive effects of the current paths of the capacitors. This limits their effectiveness to a maximum of 200 to 400 MHz. Inclusion of embedded planar capacitor laminates in the stackup have shown improvements in the overall power system impedance profile and have been shown to exhibit better noise performance. The main contributor to this superior performance is the reduced inductive effect resulting from conductive planes and thinner dielectric of the embedded laminate. This presentation discusses the performance of various embedded planar capacitor laminates in decoupling input/output (I/O) circuits. High frequency circuits were designed to demonstrate power system noise reduction and noise coupling suppression between signal traces and power-ground planes. Based on measured results, simulations for different interconnect configurations and thickness’ of embedded planar capacitor laminates were performed The presentation will describe the high frequency passive test vehicles and an active test vehicle designed to compare the simultaneous switching noise improvement of the I/O return current path. Simulations will be presented for high speed single ended and differential buses with data rates of 1Gbps, 5Gbps and 10Gbps. Power system simultaneous switching noise and signal jitter and attenuation (eye diagrams) using embedded capacitor laminates with different constructions and thickness’ will be compared.|
|Dan Amey, Research Fellow
E. I. Dupont
Research Triangle Park, NC