Abstract Preview

Here is the abstract you requested from the Passives_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Effective EMC Management of Large Size Digital Circuits and Memories Thanks to High Capacitance Density Integrated Passive Devices (IPDs)
Keywords: Integrated Passive Device, Power Integrity, Power decoupling
Power bus integrity is a continuing challenge for high performance designs in deep submicron technologies. Leading edge products with hundreds of million transistors, gigahertz clock speeds, supply voltages as low as 500-700 millivolts and supply currents of more than a hundred amps are planned at the 45nm process node. Product architecture, circuit design techniques, and process optimizations can all be used to minimize switching transients however effective supply bypass capacitance is still mandatory since power bus transients ultimately degrade product performance. Advanced silicon integrated passive technologies can now achieve capacitor densities of 250nf/mm2, enabling a variety of new possibilities to improve supply decoupling. IPD capacitor arrays can become part of a System in Package stack or used in other creative ways to position the decoupling capacitance much closer to the active switching areas of the product die (when compared to discrete decoupling capacitors positioned in/on the package or on the system PCB). Looking forward, thru-die via technologies combined with IPD technologies, will enable metal routing on both sides of the Integrated Passives die, resulting in a silicon interposer technology with built-in supply decoupling as well as the capability to integrate most of the other passive components required for the end product application. Altogether, high performance system-level ESD protection can be embedded in the same IPD at a minimum cost. Examples, such as a “one package” set top box function implemented with 3 active die and an integrated passives die containing more than 300 components will be described. Adapted novel advanced packaging methods will be presented and a method and tools will be proposed to optimize by predictability the placement and values of the components on the IPD for high efficiency power decoupling.
Jean-Marc Yannou, Innovation Manager
NXP Semiconductors
Colombelles 14906,

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems