Here is the abstract you requested from the MASH_2007 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|The Design Challenge to Integrate High Performance Organic Packaging into High End ASIC Strategic Space Based Applications|
|Keywords: Design, Packaging, Organic|
|Without a doubt, the challenge to integrate high end build up organic packaging into strategic space based applications will push the substrate fabrication and design into an area that offers the best performance, electrically, thermally and reliability that is second to none. Designing a system with dozens of ASICs and challenging the substrate design and fabrication team to produce packages that not only meet the needs of system electrical requirements and still offer robust performance as well as allowing the design team to integrate common features among a plethora of common applications is a challenge that is formidable yet not without possibilities that the Endicott Interconnect Technology first level CoreEZ packaging technology is capable of producing. The Endicott legacy of drilling 50 micron through vias at an average rate of over 200,000 vias per panel is a testament to the robustness and reliability of the technology here in Endicott. Applications with this technology have included not only high end 24/7/365 applications in a range of high end demanding server customers, but have also included customers as demanding as the Department of Defense (DOD). Many of these DOD applications have included not only a set of design parameters that most ceramic applications have been able to achieve only with increased layer count, greater weight, as well as front end NRE’s and second level interconnect reliability that is often challenged through larger packages using ceramic column grid arrays (CCGA). The capability for CoreEZ to offer high performance packaging, where signals are maintained in a full strip line environment and the low profile of the substrate cross section, as well as the capability to drill 50 micron vias on a sub 200 micron pitch within the core will allow the power distribution needs as well as the thermal dissipations requirements of the ASIC that each unique application performs as intended per DOD specifications.|
|Ronald Nowak, Senior Engineer
Endicott Interconnect Technologies
Endicott , NY